• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.359-362
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• 2010

In this study, inverter logic circuits on a plastic substrate are built with two top-gate FETs in series on a single ZnO nanowire. The voltage transfer characteristics of the ZnO nanowire-based inverter logic circuit exhibit a clear inverting operation. The logic swing, gain and transition width of the inverter logic circuit is about 90 %, 1.03 and 1.2 V, respectively. The result of mechanical bending cycles of the inverter logic circuit on a plastic substrate shows that the stable performance is maintained even after many hundreds of bending cycles.

• Research in Mathematical Education
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• v.12 no.3
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• pp.201-213
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• 2008

The main purpose of this study is to explore the relationship between the 'logical reasoning skill' and performance in the logic unit that is part of the grade 9 syllabus in mathematics in Turkey. After the teaching of the logic unit, an achievement test, a general skills test and the test of logical reasoning were administered to the 80, 9th year high school students. Pearson Moments Correlation coefficient was used for the analysis of the data to determine the relations between the variables. In addition to that to obtain the most suitable regression explaining the students' performances in the logic unit, stepwise multiple regressions analysis was used. At the end of the study, statistically significant relations were found between the students' performance in the logic unit and their logical reasoning skills, their results of the shape recognition test from the general skills battery and their overall performance in the mathematics lesson.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.785-788
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• 1993

This paper presents the prototype framework for automated integration of CMOS current-mode fuzzy logic circuits using an intelligent module approach. The library of modules representing the standard fuzzy logic operators was built. These modules were finally used to synthesized sophisticated fuzzy logic units. Fuzzy unit designs were made based upon the results of a newel methodology of the current mirror-based fuzzy logic function synthesis. This methodology is actually incorporated into the presented framework. As an example, the membership function unit was synthesized, simulated, and the final layout was generated using the presented framework. Finally, the fuzzy logic controller unit (FLC) was generated using the proposed framework. Simulation as well as measurement results show unquestionable advantages of the proposed fuzzy logic function integration system over the classical design methodology with respect to the area, relative error and performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1412-1420
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• 1999

In order to enhance multi-channel audio signals, Dolby Pro Logic is widely used especially for the Hi-Fi audio system, since it can provide highly stereophonic effects and a nice separation of multi-channel sound. This paper describes an implementation of Dolby Pro Logic decoder with ARM-7 core. The code is modified for the fixed point operation and optimized. For the verification of the code, the operation time and the precision are estimated thoroughly. As a result, it is verified that Dolby Pro Logic decoder can be implemented with ARM-7 core operating at 54 MHz.

• Proceedings of the KAIS Fall Conference
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• 2003.11a
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• pp.80-83
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• 2003

A Genetic algorithm is a searching algorithm that based on the law of the survival of the fittest. Multi-population Genetic Algorithms are a modified form of genetic algorithm. Therefore, experience with fuzzy logic and genetic algorithm has proven to be that a combination of them can efficiently make up for their own deficiency. The Multi-population Genetic Algorithms independently evolve subpopulations. In this paper, we suggest a new coding method that independently evolves subpopulations using the fuzzy logic controller. The fuzzy logic controller has applied two fuzzy logic controllers that are implemented to adaptively adjust the crossover rate and mutation rate during the optimization process. The migration scheme in the multi-population genetic algorithms using fuzzy logic controllers is tested for a function optimization problem, and compared with other group migration schemes, therefore the groups migration scheme is then performed. The results demonstrate that the migration scheme in the multi-population genetic algorithms using fuzzy logic controller has a much better performance.

• Korean Journal of Logic
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• v.21 no.3
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• pp.353-371
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• 2018

This paper deals with Routley-Meyer-style semantics, which will be called algebraic Routley-Meyer-style semantics, for the fuzzy logic system MTL. First, we recall the monoidal t-norm logic MTL and its algebraic semantics. We next introduce algebraic Routley-Meyer-style semantics for it, and also connect this semantics with algebraic semantics.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.1562-1569
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• 2008

In this paper, the study on development of an applicable logic on the characteristics of Rolling stocks will be proposed. In general, this logic which means decision logic or LTA(Logic Tree Analysis) is used to analyze how the failure mode have an effects on the system. The effect would be categorized as safety, operational, economical, etc. To do this, based on the typical logics which have been applied to other industries, such as plants, aero, etc. This paper emphasizes two crucial parameters that is one cost the other customer service, that have an important role in railway system operation. In conclusion, as mentioned above as the logic for which could be effectively applied for the railway system(RST) would be developed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.338-346
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• 1987

This paper describes a method for verifying whether a given geometrical layout correcdtly reflects the original logic level description. The logic description extracted from layout data was directly compadred with the original logic diagram generated at logic level design stage where the logic diagram is represented as a weighted multi-place graph. The comparison is based on graph isomorphism and error messages(error categories and locations)are invoked if any difference is found between the two logic descriptions. An efficient partitioning algorithm which consists of two steps, candidate selection and equal weight partitioning procedure, enables the entire verification process to occur in O(n log n) time.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.1-10
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• 1998

Partitioning problem of large combinational logic has been studied in real world. Most of logic include undectable faults from the structure of it's redundant, fan-out-reconvergent, and symetrical feature. BPT algorithm is proposed to enhance the fault voverage for combinational logic partitioning. This algorithm partitions the logic by cut the lines related to undetectable structure when seperating. Controllability and observability are considered in the process of partitioning. This algorithm is evaluated effective by testing ISCAS85 circuits.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.107-114
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• 1994

This paper describes an integrated environment for logic circuit simultion which is an important step of logic circuit design. The system consists of a logic simulator kernel, an expandible element routine library. a functional level element routine generator, several HDL input parsers, and a postprocessor. The system can simulate the same system in several levels of hierarchy. The experimental result shows that the system is very efficient and useful for design of logic circuits.