• 전기학회논문지
• /
• 제59권2호
• /
• pp.359-362
• /
• 2010

In this study, inverter logic circuits on a plastic substrate are built with two top-gate FETs in series on a single ZnO nanowire. The voltage transfer characteristics of the ZnO nanowire-based inverter logic circuit exhibit a clear inverting operation. The logic swing, gain and transition width of the inverter logic circuit is about 90 %, 1.03 and 1.2 V, respectively. The result of mechanical bending cycles of the inverter logic circuit on a plastic substrate shows that the stable performance is maintained even after many hundreds of bending cycles.

• 한국수학교육학회지시리즈D:수학교육연구
• /
• 제12권3호
• /
• pp.201-213
• /
• 2008

The main purpose of this study is to explore the relationship between the 'logical reasoning skill' and performance in the logic unit that is part of the grade 9 syllabus in mathematics in Turkey. After the teaching of the logic unit, an achievement test, a general skills test and the test of logical reasoning were administered to the 80, 9th year high school students. Pearson Moments Correlation coefficient was used for the analysis of the data to determine the relations between the variables. In addition to that to obtain the most suitable regression explaining the students' performances in the logic unit, stepwise multiple regressions analysis was used. At the end of the study, statistically significant relations were found between the students' performance in the logic unit and their logical reasoning skills, their results of the shape recognition test from the general skills battery and their overall performance in the mathematics lesson.

• 한국지능시스템학회:학술대회논문집
• /
• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
• /
• pp.785-788
• /
• 1993

This paper presents the prototype framework for automated integration of CMOS current-mode fuzzy logic circuits using an intelligent module approach. The library of modules representing the standard fuzzy logic operators was built. These modules were finally used to synthesized sophisticated fuzzy logic units. Fuzzy unit designs were made based upon the results of a newel methodology of the current mirror-based fuzzy logic function synthesis. This methodology is actually incorporated into the presented framework. As an example, the membership function unit was synthesized, simulated, and the final layout was generated using the presented framework. Finally, the fuzzy logic controller unit (FLC) was generated using the proposed framework. Simulation as well as measurement results show unquestionable advantages of the proposed fuzzy logic function integration system over the classical design methodology with respect to the area, relative error and performance.

• 한국통신학회논문지
• /
• 제24권8B호
• /
• pp.1412-1420
• /
• 1999

기존의 2 채널 stereo의 한계를 극복하고 음의 입체감을 향상시키기 위해서 2 채널 이상의 다채널로 부호화하는 기법 중에서 Dolby Pro Logic 방식은 음의 입체감이나 분리도 측면에서 매우 우수한 방법으로 고 음질을 요구하는 Hi-Fi 음향 기기에 많이 채용되고 있다. 본 논문에서는 Dolby Pro Logic 복호기를 ARM-7 코어를 사용하여 최적화를 수행하고 이의 수행 시간과 정밀도를 측정하여 구현한 code의 타당성을 입증하였다.

• 한국산학기술학회:학술대회논문집
• /
• 한국산학기술학회 2003년도 Proceeding
• /
• pp.80-83
• /
• 2003

A Genetic algorithm is a searching algorithm that based on the law of the survival of the fittest. Multi-population Genetic Algorithms are a modified form of genetic algorithm. Therefore, experience with fuzzy logic and genetic algorithm has proven to be that a combination of them can efficiently make up for their own deficiency. The Multi-population Genetic Algorithms independently evolve subpopulations. In this paper, we suggest a new coding method that independently evolves subpopulations using the fuzzy logic controller. The fuzzy logic controller has applied two fuzzy logic controllers that are implemented to adaptively adjust the crossover rate and mutation rate during the optimization process. The migration scheme in the multi-population genetic algorithms using fuzzy logic controllers is tested for a function optimization problem, and compared with other group migration schemes, therefore the groups migration scheme is then performed. The results demonstrate that the migration scheme in the multi-population genetic algorithms using fuzzy logic controller has a much better performance.

• 논리연구
• /
• 제21권3호
• /
• pp.353-371
• /
• 2018

이 글에서 우리는 대수적 루트리-마이어형 의미론이라고 불릴 의미론을 연구한다. 이를 위하여 먼저 퍼지 논리 체계 MTL과 대수적 의미론을 소개한다. 다음으로 이 체계를 위한 대수적 루트리-마이어형 의미론을 제공한 후, 이를 대수적 의미론과 연관 짓는다.

• 한국철도학회:학술대회논문집
• /
• 한국철도학회 2008년도 추계학술대회 논문집
• /
• pp.1562-1569
• /
• 2008

In this paper, the study on development of an applicable logic on the characteristics of Rolling stocks will be proposed. In general, this logic which means decision logic or LTA(Logic Tree Analysis) is used to analyze how the failure mode have an effects on the system. The effect would be categorized as safety, operational, economical, etc. To do this, based on the typical logics which have been applied to other industries, such as plants, aero, etc. This paper emphasizes two crucial parameters that is one cost the other customer service, that have an important role in railway system operation. In conclusion, as mentioned above as the logic for which could be effectively applied for the railway system(RST) would be developed.

• 대한전자공학회논문지
• /
• 제24권2호
• /
• pp.338-346
• /
• 1987

This paper describes a method for verifying whether a given geometrical layout correcdtly reflects the original logic level description. The logic description extracted from layout data was directly compadred with the original logic diagram generated at logic level design stage where the logic diagram is represented as a weighted multi-place graph. The comparison is based on graph isomorphism and error messages(error categories and locations)are invoked if any difference is found between the two logic descriptions. An efficient partitioning algorithm which consists of two steps, candidate selection and equal weight partitioning procedure, enables the entire verification process to occur in O(n log n) time.

• 전자공학회논문지C
• /
• 제35C권4호
• /
• pp.1-10
• /
• 1998

Partitioning problem of large combinational logic has been studied in real world. Most of logic include undectable faults from the structure of it's redundant, fan-out-reconvergent, and symetrical feature. BPT algorithm is proposed to enhance the fault voverage for combinational logic partitioning. This algorithm partitions the logic by cut the lines related to undetectable structure when seperating. Controllability and observability are considered in the process of partitioning. This algorithm is evaluated effective by testing ISCAS85 circuits.

• 한국시뮬레이션학회논문지
• /
• 제3권1호
• /
• pp.107-114
• /
• 1994

This paper describes an integrated environment for logic circuit simultion which is an important step of logic circuit design. The system consists of a logic simulator kernel, an expandible element routine library. a functional level element routine generator, several HDL input parsers, and a postprocessor. The system can simulate the same system in several levels of hierarchy. The experimental result shows that the system is very efficient and useful for design of logic circuits.