• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.205-214
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• 2005

Flash memory is at high speed used as storage of personal information utilities, ubiquitous computing environments, mobile phones, electronic goods, etc. This is because flash memory has the characteristics of low electronic power, non-volatile storage, high performance, physical stability, portability, and so on. However, differently from hard disks, it has a weak point that overwrites on already written block of flash memory is impossible to be done. In order to make an overwrite possible, an erase operation on the written block should be performed before the overwrite, which lowers the performance of flash memory highly. In order to solve this problem the flash memory controller maintains a system software module called the flash translation layer(FTL). Of many proposed FTL schemes, the log block buffer scheme is best known so far. This scheme uses a small number of log blocks of flash memory as a write buffer, which reduces the number of erase operations by overwrites, leading to good performance. However, this scheme shows a weakness of low page usability of log blocks. In this paper, we propose an enhanced log block buffer scheme, FAST(Full Associative Sector Translation), which improves the page usability of each log block by fully associating sectors to be written by overwrites to the entire log blocks. We also show that our FAST scheme outperforms the log block buffer scheme.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.6
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• pp.673-677
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• 2010

Recently, NAND flash memory has been widely used in embedded systems, personal computers, and server systems because of its attractive features, such as non-volatility, fast access speed, shock resistance, and low power consumption. Due to its hardware characteristics, specifically its 'erase-before-write' feature, Flash Translation Layer is required for using flash memory like hard disk drive. Many FTL schemes have been proposed, but conventional FTL schemes have problems such as block thrashing and block associativity problem. The KAST scheme tried to solve these problems by limiting the number of associations between data block and log block to K. But it has also block thrashing problem in random access I/O pattern. In this paper, we proposed a new FTL scheme, UDA-LBAST. Like KAST, the proposed scheme also limits the log block association, but does not limit data block association. So we could minimize the cost of merge operations, and reduce merge costs by using a new block reclaim scheme, log block garbage collection.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.533-536
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• 2005

MAP algorithm is known for optimal decoding algorithm of Turbo codes, but it has very large computational complexity and delay. Generally log-MAP algorithm is used in order to overcome the defect. In this paper we propose modified scheme of the state metric calculation block which can improve the computation speed in log-MAP decoder and simple linear offset unit without using LUT. The simulation results show that the operation speed of the proposed scheme is improved as compared with that of the past scheme.

• International Journal of Contents
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• v.6 no.4
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• pp.22-29
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• 2010

In flash memory, many previous garbage collection methods only merge blocks statically and do not consider the contents of buffer. These schemes may cause more unnecessary block erase operations and page copy operations. However, since flash memory has the limitation of maximum rate and life cycle to delete each block, an efficient garbage collection method to evenly wear out the flash memory region is needed. This paper proposes a memory compaction scheme based on block-level buffer for flash memory. The proposed scheme not only merges the data blocks and the corresponding log block, but also searches for the block-level buffer to find the corresponding buffer blocks. Consequently, unnecessary potential page copying operations and block erasure operations could be reduced, thereby improving the performance of flash memory and prolonging the lifetime of flash memory.

• Journal of Digital Contents Society
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• v.14 no.2
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• pp.215-222
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• 2013

NAND flash memory-based Solid State Drives (SSD) have lots of merits compared to traditional hard disk drives (HDD). However, random write in SSD is still far slower than sequential read/write and random read. There are two independent approaches to resolve this problem: 1) using part of the flash memory blocks as log blocks, and 2) using internal write buffer (DRAM or Non-Volatile RAM) in SSD. While log blocks are managed by the Flash Translation Layer (FTL), write buffer management has been treated separately from FTL. Write buffer management schemes did not use the exact status of log blocks and log block management schemes in FTL did not consider the behavior of write buffer management scheme. In this paper, we first show that log blocks and write buffer have a tight relationship to each other, which necessitates integrated management of both of them. Since log blocks also can be viewed as another type of write buffer, we can manage both of them as an integrated write buffer. Then we provide three design criteria for the integrated write buffer management scheme which can be very useful to SSD firmware designers.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.2
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• pp.90-102
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• 2010

Flash memory has been widely used as an important storage device for consumer electronics. For the flash memory-based storage systems, FTL (Flash Translation Layer) is used to handle the mapping between a logical page address and a physical page address. Especially, log buffer-based FTLs provide a good performance with small-sized mapping information. In designing the log buffer-based FTL, one important factor is to determine the mapping structure between data blocks and log blocks, called associativity. While previous works use static associativity fixed at the design time, we propose a new log block mapping scheme which adjusts associativity based on the run-time workload. Our proposed scheme improves the I/O performance about 5~16% compared to the static scheme by adjusting the associativity to provide the best performance.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.50-57
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• 1998

In this paper, we propoe a log N-stage ATM concentator. ATM concentrator is used in the ATM access network to concentrate the traffic offered at UNI, so that high utilization of the newtork rewources is achieved. The concetrator may be used as a construction block in the design of ATM switch. We define abasic element, named equalizer, and decribe its function and theory to construct an efficient concentrator using the element. In addition, a control scheme to enhance the concentrator to a superconcentrator is presented, which enables the concentration to start from an arbitrary output. This scheme makes it possible to construct an efficient ditributior or a barrel shifter which are often used in ATM switch and other application. The proposed concentrator has a low hardware complexity of O(N log N), thus it is economical to implement. Also, the time complexity of proposed concentrator for determining the rouging is O(N log N), which is faster than that of the existing ones.

• Journal of Korea Multimedia Society
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• v.12 no.12
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• pp.1710-1717
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• 2009

Flash memory has become the most important storage media in mobile devices along with its attractive features such as low power consumption, small size, light weight, and shock resistance. However, a flash memory can not be written before erased because of its erase-before-write characteristic, which lead to some garbage collection when there is not enough space to use. In this paper, we propose a novel garbage collection scheme, called block-level buffer garbage collection. When it is need to do merge operation during garbage collection, the proposed scheme does not merge the data block and corresponding log block but also search the block-level buffer to find the corresponding block which will be written to flash memory in the next future, and then decide whether merge it in advance or not. Our experimental results show that the proposed technique improves the flash performance up to 4.6% by reducing the unnecessary block erase numbers and page copy numbers.

• Journal of KIISE:Databases
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• v.36 no.5
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• pp.374-385
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• 2009

Flash memory becomes increasingly popular as data storage for various devices because of its versatile features such as non-volatility, light weight, low power consumption, and shock resistance. Flash memory, however, has some distinct characteristics that make today's disk-based database technology unsuitable, such as no in-place update and the asymmetric speed of read and write operations. As a result, most traditional disk-based database systems may not provide the best attainable performance on flash memory. To maximize the database performance on flash memory, some approaches have been proposed where only the changes made to the database, i.e., logs, are written to another empty place that has born erased in advance. In this paper, we propose an efficient log management scheme for flash-based database systems. Unlike the previous approaches, the proposed approach stores logs in specially allocated blocks, called log blocks. By evenly distributing logs across log blocks, the proposed approach can significantly reduce the number of write and erase operations. Our performance evaluation shows that the proposed approaches can improve the overall system performance by reducing the number of write and erase operation compared to the previous ones.

• The KIPS Transactions:PartA
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• v.15A no.6
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• pp.335-344
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• 2008

We propose an adaptive garbage collection technique for hybrid flash memory which has both SLC and MLC. Since SLC area is fast and MLC area has low cost, the proposed scheme utilizes the SLC area as log buffer and the MLC area as data block. Considering the high write cost of MLC flash, the garbage collection for the SLC log buffer moves a page into the MLC data block only when the page is cold or the page migration invokes a small cost. The other pages are moved within the SLC log buffer. Also it adjusts the parameter values which determine the operation of garbage collection adaptively considering I/O pattern. From the experiments, we can know that the proposed scheme provides better performance compared with the previous flash management schemes for the hybrid flash and finds the parameter values of garbage collection close to the optimal values.