• Proceedings of the IEEK Conference
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.509-510
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• 2006

FLL (Frequency Locked Loop) is the core block for high-speed transceiver. It incorporates a PLL for fine locking action, and a coarse controller for coarse locking action. A coarse controller compares frequencies coarsely and is applied to detected frequency difference directly. Compare to conventional FLL, frequency is applied to proposed FLL. Proposed FLL in this paper achieves only 5 cycles for coarse lock and total frequency locking time is 5 times faster than conventional FLL. Thus, proposed FLL is more useful to Ethernet transceiver application that requires high-speed data transfer than conventional FLL. Proposed FLL is based on $0.18{\mu}m$ process.

• The KIPS Transactions:PartA
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• 제10A권3호
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• 제3권2호
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• pp.69-74
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• 2004

In this work, A PLDRO (Phase Locked Dielectric Resonator Oscillator) which can be used for the wireless communication systems fur MMC(Microwave Micro Cell) and ITS wireless communication system is designed. A different approach to the PLDRO structure is applied for phase locking by dual phase lock loop structure. The proposed dual loop PLDRO generates the output power of 0 dBm at 18.7 GHz and has the characteristics of a phase noise of -80 dBc/Hz at 1kHz, -83 dBc/Hz at 10 kHz offset frequency from carrier frequency

• Transactions of the Korean Society of Mechanical Engineers B
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• 제24권1호
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• pp.75-84
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• 2000

Performance and flow characteristics of a small forward swept propeller fan for home refrigerators are studied experimentally. An unusual discontinuity is observed in the performance curve of the fan. Mean flow fields measured with as-hole Pitot probe reveal that the flow is axial at the high flow rate and radial at the low flow rate. The flow structure changes abruptly across the discontinuity. Unsteady flow measurements with a set of hot-wire probes indicate that near the discontinuity a single-cell stall rotates at 40% speed of the fan speed, while away from the discontinuity the flow shows periodic variation corresponding to the blade passage frequency. Phase-lock averaged flow fields measured with a triple-sensor hot-wire probe show that there appears radially inward flow over the pressure side of the blade and the outward passage flow over the tip.

• The Journal of the Korea institute of electronic communication sciences
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• 제4권4호
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• pp.247-252
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• 2009

This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).

• Proceedings of the KIPE Conference
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• 전력전자학회 2013년도 전력전자학술대회 논문집
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• pp.47-48
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• 2013

In order to evaluate the response of the grid-connected systems, Phase lock technology is widely used in power electronic devices to obtain the phase angle, amplitude, and frequency of the grid voltage because phase locked loop (PLL) algorithms are very important for grid synchronization and monitoring in the grid connected power electronic devices. This paper presents a performance evaluation in tracking grid angular frequency through single phase synchronization techniques which are an enhanced PLL (EPLL), second-order generalized integrator-PLL (SOGI-PLL), and second-order generalized integrator-frequency locked loop (SOGI-FLL). These techniques are properly analyzed through several steps to get the best technique which can track the frequency accurately and smoothly.

• Journal of Institute of Control, Robotics and Systems
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• 제7권8호
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• pp.697-702
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• 2001

The ring laser gyro(RLG) has been used extensively in strapdown inertial navigation system(SDINS) because of the apparent of having wide dynamic range, digital output and high accuracy. The dithered RLG system has dynamic motion at sensor level, caused by the dithering motion to overcome the lock-in threshold. In this case, an attitude error is produced by not only the true coning of the vehicle motion but also the pseudo coning of the sensor motion. This paper describes the definition of the multi-frequency coning motion and its noncommutativity error to reject the pseudo coning error produced by the sensor motion such as the dithered RLG. The simulation results are presented to minimize the multi-frequency coning error.

• The Transactions of the Korean Institute of Electrical Engineers C
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• 제53권11호
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• pp.583-588
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• 2004

We stabilized the frequency and power of a high voltage excited CW CO2 laser on the peak of the Doppler broadened gain curve using the photoacoustic effect generated from the laser itself. The photoacoustic signal is directly coupled from an radio frequency discharge chamber via a capacitor microphone into a detector and a lock-in stabilizer. The frequency stability is estimated to be better then 1.2×10/sup -7/ at the transition P(20) line. The stabilized output power variation was reduced to from 77 % to 3.3 %.

• Wind and Structures
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• 제21권5호
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• pp.523-536
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• 2015

To study the vibration frequency of super high-rise buildings in the process of vortex induced vibration (VIV), wind tunnel tests of multi-degree-of-freedom (MDOF) aero-elastic models were carried out to measure the vibration frequency of the system directly. The effects of structural damping, wind field category, mass density, reduced wind velocity ($V_r$), as well as VIV displacement on the VIV frequency were investigated systematically. It was found that the frequency drift phenomenon cannot be ignored when the building is very high and flexible. When $V_r$ is less than 8, the drift magnitude of the frequency is typically positive. When $V_r$ is close to the critical wind velocity of resonance, the frequency drift magnitude becomes negative and reaches a minimum at the critical wind velocity. When $V_r$ is larger than12, the frequency drift magnitude almost maintains a stable value that is slightly smaller than the fundamental frequency of the aero-elastic model. Furthermore, the vibration frequency does not lock in the vortex shedding frequency completely, and it can even be significantly modified by the vortex shedding frequency when the reduced wind velocity is close to 10.5.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제60권2호
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.