• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.37 no.3
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• pp.275-282
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• 2009

Generally, the sinusoidal cavity dither is adopted to ring laser gyroscope for eliminating the lock-in which is non-linear effect at the small rotation input. Despite this method, there are some remained errors which are generated at the dither turnaround, and those errors produce random walk which is a general character of a ring laser gyroscope. As one of the numerous research results for compensating these errors, there is a special lock-in compensation method which is the method of error estimation and compensation by comparing the beat signal periods of before and after the dither turnarounds. In this paper, by ring laser gyroscope modeling and numerical analysis, we verified the theoretical validity and confirmed the effectiveness of this method in expectation of the possible beat signal measurement time resolution. As a result, we confirmed the random walk decreases from a-half to a-third by this lock-in compensation method. So, it is expected to be a remarkable method for reducing the INS alignment time.

• Journal of the Korea Institute of Military Science and Technology
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• v.2 no.1
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• pp.139-149
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• 1999

In this paper, we estimate the scale factor error and random walk characteristics of the ring laser gyro which has the body dither for Lock-in compensation. And then, we compared those results with the static test results for 28cm square ring laser gyro which has about 0.5 deg/sec static Lock-in. In the case of sinusoidal body dither, dynamic Lock-in occurs periodically at the points where the gyro output pulse becomes the integer multiples of body dither frequency. The width of dynamic Lock-in is changed by variation of dither amplitude, and, between the width of dynamic Lock-in which occurs at the even multiple points of body dither frequency and that at the odd muliple points of body dither frequency, it has 180o phase difference. Generally random body dither is adopted to compensate for dynamic Lock-in. Then if the irregularity is not large enough, the scale factor error by dynamic Lock-in is not vanished. And if the irregularity is large enough, the scale factor error decreases, but random walk becomes larger relatively. And we confirmed that the larger body dither amplitude, the smaller random walk.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.410-415
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• 2011

In this paper, we investigated the fault current limiting and the load voltage sag suppressing characteristics of the flux-lock type SFCL, designed with the additive polarity winding, according to the variations of turn number's ratio and the comparative analysis between the resistive type and the flux-lock type SFCLs were performed as well. From the analysis for the short-circuit tests, the flux-lock type SFCL designed with the larger turn number's ratio was shown to perform more effective fault current limiting and load voltage sag suppressing operations compared to the flux-lock type SFCL designed with the lower turn number's ratio through the fast quench occurrence of the high-$T_C$ superconducting (HTSC) element comprising the flux-lock type SFCL. In addition, the recovery time of the flux-lock type SFCL after the fault removed could be confirmed to be shorter in case of the flux-lock type SFCL designed with the lower turn number ratio.

• Korean Journal of Optics and Photonics
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• v.34 no.2
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• pp.76-83
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• 2023

In this paper, the results of analyzing the frequency lock-in breaking characteristics of a ring laser gyroscope with random dithering through numerical experiments are presented. By observing the variant features in the frequency lock-in characteristics according to the dithering amplitude noise, it was possible to analyze the minimum noise condition that causes the frequency lock-in to be broken. It was confirmed that the result is closely related to the relative difference between the dynamic frequency lock-in corresponding to the average dithering amplitude and the frequency determined by the Sagnac effect corresponding to an input rotational angular velocity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11A
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• pp.882-890
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• 2009

In this paper, we describe a compensation method that can be used for the situation where Loran receivers lose their phase lock to the received Loran signals when Loran signals are employed for the synchronization of national infrastructures such as telecommunication networks, electric power distribution and so on. In losing the phase lock to the received signals in a Loran receiver, the inner oscillator of the receiver starts free-running and the performance of the timing synchronization signals which are locked to the oscillator's phase is very severly degraded, so the timing accuracy under 1 us for a Primary Reference Clock (PRC) required in the International Telecommunications Union (ITU) G.811 standard can not be satisfied in the situation. Therefore, in this paper, we propose a method which can compensate the phase jump by using a compensation algorithm when a Loran receiver loses its phase lock and the performance evaluation of the proposed algorithm is achieved by the Maximum Time Interval Error (MTIE) of the measured data. From the performance evaluation results, it is observed that the requirement under 1 us for a PRC can be easily achieved by using the proposed algorithm showing about 0.6 us with under 30 minutes mean interval of smoothing with 1 hour period when the loss of phase lock occurs.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1771-1772
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• 2008

전동기나 발전기와 같은 회전기기에 주로 발생하는 주기외란은 시스템 성능을 저하시키는 특성으로서 고급제어시스템 구현을 위하여 반드시 보상되어야 한다. 본 논문은 신호처리기법의 일종인 Lock In Amplifier(LIA) 알고리즘 기반 외란보상 제어기를 제안한다. 제안하는 제어규칙은 공칭제어기와 보조제어기로 구성되며 전자는 외란을 고려하지 않은 시스템 모델에 대하여 상태궤환 제어기법으로 산출되며 후자는 LIA 기법을 이용하여 외란특성을 실시간으로 추정하여 연산되어진다. 제안하는 제어시스템은 기존의 결정적 외란으로부터 발생되었던 실시간 제어오차를 월등히 개선하는 장점을 가지고 있다. 실시간 전동기 제어장치를 통해 제안하는 알고리즘의 성능의 우수성 및 타당성을 검증한다.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.12
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• pp.1000-1003
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• 2012

The superconducting fault current limiter (SFCL) can quickly limit the fault current shortly after the short circuit occurs and recover the superconducting state after the fault removes and plays a role in compensating the voltage sag of the sound feeder adjacent to the fault feeder as well as the fault current limiting operation of the fault feeder. Especially, the flux-lock type SFCL with an isolated transformer, which consists of two parallel connected coils on an iron core and the isolated transformer connected in series with one of two coils, has different voltage sag compensating and current limiting characteristics due to the winding direction and the inductance ratio of two coils. The current limiting and the voltage sag compensating characteristics of a SFCL using a transformer winding were analyzed. Through the analysis on the short-circuit tests results considering the winding direction of two coils, the SFCL designed with the additive polarity winding has shown the higher limited fault current than the SFCL designed with the subtractive polarity winding. It could be confirmed that the higher fault current limitation of the SFCL could be contributed to the higher load voltage sag compensation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.47 no.5
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• pp.358-363
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• 2019

If the EOIR equipment mounted on an unmanned aircraft transmits images and receives commands through a data link, there may be delays in data transmission depending on the transmission path of the data and the conditions of the ground equipment or wireless network. This increases the possibility of initial target LOCK-ON failure due to the difference between the time when the received image is viewed and the time when the image is taken. Therefore, this paper proposed a way to use frame indexes to synchronize with images, and to increase the success of target tracking by adding frame indexes to commands from the ground station.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.4
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• pp.195-200
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• 2006

The conventional discrete circuit for ABS/TCS system was examined and the problems of the system were analyzed by computer simulation. In order to improve the performance of ABS/TCS system, interface IC which has error compensation, comparator and under voltage lock-out circuit was designed and their electrical characteristics were investigated. The voltage regulator was included to compensate the temperature variation in the temperature range from $-20^{\circ}C$ to $120^{\circ}C$ for automobile environment. ABS and brake signal were separated using the duty factor of same frequency or different frequencies. UVLO(Under Voltage Lock-Out) circuit and constant current circuit were applied for the elimination of noise, and protection circuit was applied to cut the excess current off. Layout for IC fabrication was designed to enhance the electrical performance of ABS/TCS system. Layout was consisted of 11 masks, arrayed effectively 8 pads to reduce the current loss. We can see that the result of layout simulation was better than the result of bread board.