• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
• /
• v.36 no.4
• /
• pp.255-262
• /
• 2018

In order to determine the three-dimensional position in photogrammetry, a spatial resection is a pre-requisite step to determine exterior orientation parameters. The existing spatial resection method is a non-linear equation that requires initial values of exterior orientation parameters and has a problem that a gimbal lock phenomenon may occur. On the other hand, the spatial resection using quaternion is a closed form solution that does not require initial values of EOP (Exterior Orientation Parameters) and is a method that can eliminate the problem of gimbal lock. In this study, to analyze the stability of the quaternion-based spatial resection, the exterior orientation parameters were determined according to the different layout of control points and were compared with the determined values using existing non-linear equation. As a result, it can be seen that the quaternionbased spatial resection is affected by the layout of the control points. Therefore, if the initial value of exterior orientation parameters could not be obtained, it would be more effective to estimate the initial exterior orientation values using the quaternion-based spatial resection and apply it to the collinearity equation-based spatial resection method.

• Journal of Internet Computing and Services
• /
• v.1 no.2
• /
• pp.11-18
• /
• 2000

In this paper we present a new extensible model based upon the concept of subtransactions in real-time transaction systems. The nested transaction model originally proposed by J. Moss is extended for real-time uniprocessor transaction systems by adding explicit timing constraints. Based upon the model, an integrated concurrency control and scheduling algorithm is developed, that not only guarantees timing constraints of a set of real-time transactions but also maintains consistency of the database. The algorithm is based on the priority ceiling protocol of Sha et al. We prove that the Real-Time Nested Priority Ceiling Protocol prevents unbounded blocking and deadlock, and maintains the serializability of a set of real-time transactions. We use the upper bound on the duration that a transaction can be blocked to show that it is possible to analyze the schedulability of a transaction set using rate-monotonic priority assignment. This work is viewed as a step toward multiprocessor and distributed real-time nested transaction systems. Also, it is possible to be extended to include the real-time multimedia transactions in the emerging web-based database application areas.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.8
• /
• pp.1780-1784
• /
• 2015

Traditional IP routing, see only the Destination Address When Forwarding Layer 3 routing and exchange information and Destination-Based Routing Lookup is required for all Hop. Thus, all routers Full Internet routing information, the route information of more than about 120,000 may require. Therefore, the router configuration, which can be dispersed in the environment, the traffic load is required in accordance with this congestion. In this study, a unique characteristic of the Internet in the environment of an existing network Best Effect for QoS guarantee and hardware high speed switching of large multimedia data transmitted using a Labeling for forwarding a packet environment configuration is required. Video Stream Broadcast Transport Labeling rather than in much of the higher performance of the multi-step policy to most of the Video Stream Packet deulim was fixed to Labeling Header Format proposes a method of applying an effective QoS policy to a more simplified policy.

• Smart Structures and Systems
• /
• v.24 no.6
• /
• pp.709-721
• /
• 2019

This paper investigates the framework of vision-based dense displacement and strain measurement of miter gates with the approach for the quantitative evaluation of the expected performance. The proposed framework consists of the following steps: (i) Estimation of 3D displacement and strain from images before and after deformation (water-fill event), (ii) evaluation of the expected performance of the measurement, and (iii) selection of measurement setting with the highest expected accuracy. The framework first estimates the full-field optical flow between the images before and after water-fill event, and project the flow to the finite element (FE) model to estimate the 3D displacement and strain. Then, the expected displacement/strain estimation accuracy is evaluated at each node/element of the FE model. Finally, methods and measurement settings with the highest expected accuracy are selected to achieve the best results from the field measurement. A physics-based graphics model (PBGM) of miter gates of the Greenup Lock and Dam with the updated texturing step is used to simulate the vision-based measurements in a photo-realistic environment and evaluate the expected performance of different measurement plans (camera properties, camera placement, post-processing algorithms). The framework investigated in this paper can be used to analyze and optimize the performance of the measurement with different camera placement and post-processing steps prior to the field test.

• International Journal of Naval Architecture and Ocean Engineering
• /
• v.12 no.1
• /
• pp.491-500
• /
• 2020

The present study proposes a time domain model for the Vortex-induced Vibration (VIV) simulation of a catenary riser under the combination of the current and oscillatory flow induced by vessel motion. In this model, the hydrodynamic force of VIV comprises excitation force, hydrodynamic damping and added mass, which are taken as functions of the non-dimensional frequency and amplitude ratio. The non-dimensional frequency is related with the response frequency, natural frequency, lock-in range and the fluid velocity. The relatively oscillatory flow induced by vessel motion is taken into account in the fluid velocity. Considering that the added mass coefficient and the non-dimensional frequency can affect each other, an iterative analysis is conducted at each time step to update the added mass coefficient and the natural frequency. This model is in detail validated against the published test models. The results show that the model can reasonably reflect the effect of the added mass coefficient on the VIV, and can well predict the riser's VIV under stationary and oscillatory flow induced by vessel motion. Based on the model, this study carries out the VIV simulation of a catenary riser with harmonic vessel motion. By analyzing the bending moment near the touchdown point, it is found that under the combination of the ocean current and oscillatory flow the vessel motion may decrease the VIV response, while increase the excited frequencies. In addition, the decreasing rate of the VIV under vessel surge is larger than that under vessel heave at small vessel motion velocity, while the situation becomes opposite at large vessel motion velocity.

• Journal of IKEEE
• /
• v.14 no.1
• /
• pp.65-74
• /
• 2010

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.10C
• /
• pp.1032-1041
• /
• 2007

The global navigation satellite system (GNSS), which is the core technique for the location based service, adopts the direct sequence/spread spectrum (DS/SS) as its modulation method. The success of a DS/SS system depends on the synchronization between the received and locally generated pseudo noise (PN) signals. As a step in the synchronization process, the tacking scheme performs fine adjustment to bring the phase difference between the two PN signals to zero. The most widely used tracking scheme is the delay locked loop with early minus late discriminator (EL-DLL). In the ideal case, the EL-DLL is the best estimator among various DLL. However, in the band-limited multipath environment, the EL-DLL has tracking bias. In this paper, the timing offset range of correlation function is divided into advanced offset range (AOR) and delayed offset range (DOR) centering around the correct synchronization time point. The tracking bias results from the following two reasons: symmetry distortion between correlation values in AOR and DOR, and mismatch between the time point corresponding to the maximum correlation value and the synchronization time point. The former and latter are named as the type I and type II tracking bias, respectively. In this paper, when the receiver has finite bandwidth in the presence of multipath signals, it is shown that the type II tracking bias becomes a more dominant error factor than the type I tracking bias, and the correlation values in AOR are not almost changed. Exploiting these characteristics, we propose a novel tracking bias mitigation scheme and demonstrate that the tracking accuracy of the proposed scheme is higher than that of the conventional scheme, both in the presence and absence of noise.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.6C
• /
• pp.505-511
• /
• 2008

The global navigation satellite system (GNSS) is using a direct sequence/spread spectrum (DS/SS) modulation. In order to recover the information data, the DS/SS system first performs a two-step synchronization process: acquisition and tracking. The acquisition process adjusts the phase difference between the received and locally generated acquisition sequences within ${\pm}T_c/2$ or less, where $T_c$ is the chip period. The tracking process performs fine synchronization. In this paper, we focus on the tracking issue. The single delta delay locked loop($\Delta$-DLL) is the optimal tracking scheme for a GNSS in the absence of multipath signals, where $\Delta$ means the spacing between the early and late correlation time offset. In the multipath environments, however, the $\Delta$-DLL suffers from huge estimation bias(denoted by $\beta$) caused by distorted correlation values. Although some modified schemes such as a $\Delta$-DLL with a narrow $\Delta$ and a double delta DLL (${\Delta}^{(2)}$-DLL) were proposed to reduce the estimation bias, they cannot remove the estimation bias completely and need more accurate acquisition process. This paper proposes a novel tracking scheme that can dramatically reduce the estimation bias, using the maximum slope change among the correlation outputs.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.9
• /
• pp.21-26
• /
• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.