• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.6
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• pp.21-28
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• 2008

In this paper, we proposed an algorithm that reduces call setup time between the IP PBXs installed in the main office and several branch offices. In the IP PBXs installed in branch offices, we prepare some internal memory spaces, and they keep the frequently used extension numbers and the corresponding IP PBX's addresses. In order to call an extension number registered to the other remote IP PBX from an extension number registered to the local IP PBX, the local PBX searches for the destined extension from its internal memory first. If the extension is found, then the local PBX uses its corresponding IP PBX address stored along with the extension, instead of making a query to the main office's IP PBX. By this technique, we could shorten the average call setup time and verified it by an experiment.

• Journal of Korean Society of Archives and Records Management
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• v.20 no.3
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• pp.161-166
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• 2020

"Gyeonggi-do Memory," established and operated by Gyeonggi-do Cyber Library, is a local digital archive aiming to broaden the access to Gyeonggi-do's cultural resource records. Since 2014, the library has been expanding its digital information service, starting with the said archive. Through cooperation with various cultural institutions in the province, it builds the digital archive by collecting numerous records. In particular, the archive is expected to establish itself as a repository that stores records of production or dealing in Gyeonggi-do and a platform to share with researchers and citizens.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.223-228
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• 2005

Several researchers have pointed out that the energy consumption in memory takes a dominant fraction on the energy budget of a whole embedded system. This applies to the embedded Java virtual machine tn, and to develop a more energy-efficient JVM it is absolutely necessary to optimize the energy usage in Jana memory. In this paper we have analyzed the logical memory access pattern in JVM as it executes numerous number of bytecode instructions while running a Java program. The access pattern gives us an insight how to design and select a suitable memory technology for Java memory. We present the memory access pattern for the three logical data spaces of JVM: heap, operand stack, and local variable array. The result saws that operand stack is accessed most frequently and uniformly, whereas heap used least frequently and non-uniformly among the three. Both heap and local variable array are accessed mostly in read-only fashion, but no remarkable difference is found between read and write operations for operand stack usage.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.806-809
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• 2007

SRAM cell array and peripheral circuits on display panel are designed using LTPS process. To overcome low yield of SOP, high speed parallel fault detection circuitry for memory cells is designed at local I/O lines with minimal overhead for efficient memory cell redundancy replacement. Normal read/write and parallel test read/write are simulated and verified.

• Bulletin of the Korean Chemical Society
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• v.12 no.4
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• pp.423-429
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• 1991

Global and local memory functions, defined by Quack and Troe, were calculated for the rotationally inelastic collision of O + SO(v, j)→ [O--S--O]→O + SO(v, j'). It is seen to decrease steadily as total energy increases. Distribution of scattering cross section over product rotational states also shows the decreasing memory of initial state as total energy is increased. These results are interpreted in terms of energy scrambling at high energy due to the availability of more phase space and also the influence of strong dynamical constraints.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2003.05a
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• pp.105-108
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• 2003

The local motion at the top of an A-frame fixed on a research vessel for deep sea ROV floating in irregular waves is studied in the time-domain. The motion is analyzed in the time-domain using the convolution integral of the radiation forces. The memory effect functions and infinite frequency added masses are obtained from the solution of the three dimensional improved Green integral equation in the frequency domain by making use of the Fourier transformation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.1-10
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• 2008

In this paper, we describe a design of a 128bit MRAM based on a new switching architecture which is Local Field Switching(LFS). LFS uses a local magnetic field generated by the current flowing through an MTJ. This mode reduces the writing current since small current can induce large magnetic field because of close distance between MTJ and the current. It also improves the cell selectivity over using conventional MTJ architecture because it doesn't need a digit line for writing. The MRAM has 1-Transistor 1-Magnetic Tunnel Junction (IT-1MTJ) memory cell structure and uses a bidirectional write driver, a mid-point reference cell block and a current mode sense amplifier. CMOS emulation cell is adopted as an LFS-MTJ cell to verify the operation of the circuit without the MTJ process. The memory circuit is fabricated using a $0.18{\mu}m$ CMOS technology with six layers o) metal and tested on custom board.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.11a
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• pp.52-53
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• 2012

Belief propagation (BP) is a commonly used global energy minimization algorithm for solving stereo matching problem in 3D reconstruction. However, it requires large memory bandwidth and data size. In this paper, we propose a novel memory-efficient algorithm of BP in stereo matching on the Graphics Processing Units (GPU). The data size and transfer bandwidth are significantly reduced by storing only a part of the whole message. In order to maintain the accuracy of the matching result, the local messages are reconstructed using shared memory available in GPU. Experimental result shows that there is almost an order of reduction in the global memory consumption, and 21 to 46% saving in memory bandwidth when compared to the conventional algorithm. The implementation result on a recent GPU shows that we can obtain 22.8 times speedup in execution time compared to the execution on CPU.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.258-262
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

• ETRI Journal
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• v.44 no.3
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• pp.450-461
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• 2022

The Gen-Z protocol is a memory semantic protocol between the memory and CPU used in computer architectures with large memory pools. This study presents the implementation of the Gen-Z hardware system configured using Gen-Z specification 1.0 and reports its performance. A hardware prototype of a DDR4 Gen-Z memory pool with an optimized character, a block device driver, and a file system for the Gen-Z hardware was designed. The Gen-Z IP was targeted to the FPGA, and a 512 GB Gen-Z memory pool was configured on an ×86 server. In the experiments, the latency and throughput of the Gen-Z memory were measured and compared with those of the local memory, SATA SSD, and NVMe using character or block device interfaces. The Gen-Z hardware exhibited superior throughput and latency performance compared with SATA SSD and NVMe at block sizes under 4 kB. The MySQL and File IO benchmark of Gen-Z showed good write performance in all block sizes and threads. Besides, it showed low latency in RocksDB's fillseq dbbench using the ext4 direct access filesystem.