• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.921-930
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• 2016

This paper proposes a design and control method for a high-voltage direction current modular multilevel converter (HVDC-MMC) considering the capacitor voltage ripple of the submodule (SM). The capacitor voltage ripple consists of the line frequency and double-line-frequency components. The double line- frequency component does not fluctuate according to the active power, whereas the line-frequency component is highly influenced by the grid-side voltage and current. If the grid voltage drops, a conventional converter increases the current to maintain the active power. A grid voltage drops, current increment, or both occur with a capacitor voltage ripple higher than the limit value. In order to reliably control an MMC within a limit value, the SM capacitor should be designed on the basis of the capacitor voltage ripple. In this paper, the capacitor voltage ripple according to the grid voltage and current are analyzed, and the proposed control method includes a current limitation method considering the capacitor voltage ripple. The proposed design and control method are verified through simulation using PSCAD/EMTDC.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.347-349
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• 2013

This paper describes analysis and calculation of line frequency ripple current according to output capacitor value and effects of LED connection in the single stage flyback converter with high power factor. The low frequency output ripple current delivered from single stage converter has been analyzed in detail and the method evaluating parasitic resistance included in LED has been provided. In order to verify the equation derived in this paper, the single stage flyback converter has been designed with constant output current regulation with DCM operation. Experiments were conducted with different LED load structures to analyze the effect of LED parasitic resistance on output ripple current. As test results, the calculation can provide guide line to select capacitor values depending on output ripple current and LED characteristics.

• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1251-1264
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• 2018

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.968-969
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• 2015

This paper proposes a novel analysis method for calculating inverter DC bus capacitance and line reactor parameters. In the realization process, DC bus capacitance parameter, and ripple current, life of DC bus capacitor, interaction between DC bus capacitance can be calculated by using Newton-Raphson procedure. The design scheme of DC bus capacitor and line reactor, specific parameters such as capacitance, loss, ripple current, central average temperature, life, ripple current, loss, size, central temperature of the reactor were given. Simulation results show that this scheme can accurately calculate the DC bus capacitance and line reactor parameters. Compared with calculation result of references, cost and volume are half. The indicators meet the demand of practical engineering. It had affirmed precision of the analytical method and verified correctness and feasibility of this method.

• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.152-155
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• 2009

In high power application, PFC(Power Factor Correction) pre-regulators are generally required. PFC pre-regulators could achieve unity power factor, reduce line input current harmonics and utilize full line power. Interleaving PFC converters could reduce input ripple current, output capacitor ripple current and inductor size. With this closed loop interleaving method, both two phase converters are working at the boundary between continuous and discontinuous mode and accurate 180 degree phase shift is achieved. Implementation of this strategy could be easily integrated to the control chip. Finally, experimental results of a two-phase interleaved boost PFC are presented to verify the discussed features.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.974-976
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• 2001

This paper presents a method to reduce commutation torque ripples occurred during commutation in brushless do motor drives using a single DC-link current sensor. In brushless dc motor drives with a single dc current sensor instead of 3-phase line current sensors, it is noted that dc-link current sensor cannot give any information corresponding to the motor currents during line current commutation intervals. A new technique to resolve such a problem is dealt with based on a deadbeat current control in which motor armature voltage command is computed from a dc-link current reference, an actual current and counter emf voltage. The simulation results show that the proposed method reduces the torque ripple significantly.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.247-250
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• 1995

This paper proposes a new method to reduce the torque ripple in vector controlled inverter fed synchronous motor systems. In three phase voltage source inverter systems, all the three line currents are generally not measured and the currents of two lines are measured through two sensors and two A/D converters. The measured currents may contain some error due to the non-ideality of the current sensors and A/D converters, and the error coefficient of two line currents are not same. As a result, the developed torque contains the torque ripple. The proposed method can eliminate the torque ripple by setting the error coefficient to same value. To verify the proposed method, digital simulations are carried out.

• Proceedings of the KSR Conference
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• 2005.05a
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• pp.800-805
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• 2005

In this study, control schemes are proposed for a propulsion system of TTX(Tilting Train eXpress). In developed traction converter, unity power factor control, compensation method of dc link voltage have been applied. Output current of converter contains harmonic ripple at twice input ac line frequency, which causes a ripple in the dc link voltage so that beatless control is developed in inverter system to reduce the pulsating torque current. This system is verified by the system modelling and prototype test.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.73-78
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• 2020

In this study, a novel reactive power control scheme is proposed to supply stable reactive power to the distribution line by compensating a ripple voltage of DC link. In a single-phase system, a magnitude of second harmonic is inevitably generated in the DC link voltage, and this phenomenon is further increased when the capacity of DC link capacitor decreases. Reactive power control was performed by controlling the d-axis current in the virtual synchronous reference frame, and the voltage control for maintaining the DC link voltage was implemented through the q-axis current control. The proposed method for compensating the ripple voltage was classified into three parts, which consist of the extraction unit of DC link voltage, high pass filter (HPF), and time delay unit. HPF removes an offset component of DC link voltage extracted from integral, and a time delay unit compensates the phase leading effect due to the HPF. The compensated DC voltage is used as feedback component of voltage control loop to supply stable reactive power. The performance of the proposed algorithm was verified through simulation and experiments. At DC link capacitance of 375 uF, the magnitude of ripple voltage decreased to 8 Vpp from 74 Vpp in the voltage control loop, and the total harmonic distortion of the current was improved.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.223-226
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• 2001

In this paper, dc link ripple currents for three-phase ac/dc/ac PWM converters are analyzed in a frequency domain. The expression of the harmonic currents is developed by using switching functions and exponential Fourier series expansion. The dc link ripple currents with regard to power factor and modulation index are investigated. In addition, the effect of the displacement angle between the switching periods of line-side converters and load-side inverters on the do link ripple current is studied. The result of the do link current analysis is helpful in specifying the dc link capacitor size and its life time estimation.