• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.80-86
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• 2002

This paper presents a fast hardware architecture to implement a 2-D DWT(Discrete Wavelet Transform) computed by lifting scheme framework. The conventional 2-D DWT hardware architecture has problem in internal memory, hardware resource, and latency. The proposed architecture was based on the 4-way partitioned data set. This architecture is configured with a pipelining parallel architecture for 4-way partitioning method. Due to the use of this architecture, total latency was improved by 50%, and memory size was reduced by using lifting scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.97-104
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• 2004

This paper proposes an efficient VLSI architecture of 9-7/5-3 Lifting DWT filters that is used by lossy or lossless compression of JPEG2000. The proposed architecture uses only internal line memories to compute Lifting-DWT operations and its PE(Processing Element) has critical path with 1 multiplier and 1 adder. To reduce the number of PE, we make the vertical filter that is responsible for the column operations of the first level perform both the row and column operations of the second and following levels. As a result, the architecture has smaller hardware cost compared to that of other architectures. It was modeled in RTL level using VHDL and implemented on Altera APEX 20K FPGA.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.91-101
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• 2012

DNA watermarking have been interested for both the security of private genetic information or huge DNA storage information and the copyright protection of GMO. Multimedia watermarking has been mainly designed on the basis of frequency domain, such as DCT, DWT, FMT, and so on, for the robustness and invisibility. But a frequency domain watermarking for coding DNA sequence has a considerable constraint for embedding the watermark because transform and inverse transform must be performed without completely changing the amino acid sequence. This paper presents a coding sequence watermarking on lifting based DWT domain and brings up the availability of frequency domain watermarking for DNA sequence. From experimental results, we verified that the proposed scheme has the robustness to until a combination of 10% point mutations, 5% insertion and deletion mutations and also the amino preservation and the security.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.883-886
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• 2003

본 논문에서는 Lifting-Based Scheme을 이용한 DWT(Discrete Wavelet Transform) 의 개선된 행 처리기의 구조를 제안 하였다. 제안된 행 처리기는 3개의 Adder 와 2개의 shifter를 사용 하였고 dual-port RAM을 사용하여 파이프 라인 구조를 취하여 각 클럭마다 열처리기에서 사용할 데이터를 발생 한다. 이러한 행 처리기의 파이프 라인 구조를 개선하여 Adder를 줄이고 행 처리기의 이용률을 최대로 하여 하드웨어의 공간적 비용 절감 효과를 가져 왔다. 제안된 구조는 Verilog를 사용하여 RTL설계를 한뒤 시뮬레이션으로 그 동작을 확인 하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.518-525
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• 2003

In this paper, we present a fast hardware architecture to implement a parallel 2-dimensional discrete wavelet transform(DWT)based on the lifting scheme DWT framework. The conventional 2-D DWT had a long initial and total latencies to get the final 2D transformed coefficients because the DWT used an entire input data set for the transformation and transformed sequentially The proposed architecture increased the parallel performance at computing the row directional transform using new data splitting method. And, we used the hardware resource sharing architecture for improving the total throughput of 2D DWT. Finally, we proposed a scheduling of hardware resource which is optimized to the proposed hardware architecture and splitting method. Due to the use of the proposed architecture, the parallel computing efficiency is increased. This architecture shows the initial and total latencies are improved by 50% and 66%.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2315-2318
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• 2003

The Wavelet Transform has been applied in mathematics and computer sciences. Numerous studies have proven its advantages in image processing and data compression, and have made it a basic encoding technique in data compression standards like JPEG2000 and MPEG-4. Software implementations of the Discrete Wavelet Transform (DWT) appears to be the performance bottleneck in real-time systems in terms of performance. And hardware implementations are not flexible. Therefore, FPGA implementations of the DWT has been a topic of recent research. The goal of this thesis is to investigate of FPGA implementations of the DWT Processor for image compression applications. The DWT processor design is based on the Lifting Based Wavelet Transform Scheme, which is a fast implementation of the DWT The design uses various techniques. The DWT Processor was simulated and implemented in a FLEX FPGA platform of Altera

• Journal of Broadcast Engineering
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• v.6 no.1
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• pp.32-40
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• 2001

In this paper, we propose a DWT (discrete Wavelet Transform) based watermarking method, which can be conveniently Integrated In the up-coming JPEG2770 baseline system. Although Conventional DWT based watermarking techniques insert watermark signal Into wavelet coefficients after the transform, our proposed method embeds a watermark into wavelet coefficients obtained from the ongoing process of lifting for DWT. The proposed method allows us to selectively determine frequency characteristics of the coefficients where the watermark is embedded. so that the Inserted watermark cannot be removed or altered even when the filter-bank for DWT is known. Through the simulation, we show that the proposed method is more secure and more robust against various attacks than conventional DWT barred watermarking techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.993-1000
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• 2012

In this research, we proposed an efficient VLSI architecture of the lifting-based 2D DWT (Discrete Wavelet Transform) filter with 100% hardware utilization. The (9,7) filter structure has been applied and extendable to the filter length. We proposed a new block-based scheduling that computes the DWT for the lower levels on an "as-early-as-possible" basis, which means that the calculation for the lower level will start as soon as the data is ready. Since the proposed 2D DWT computes the outputs of all levels by one row-based scan, the intermediate results for other resolution levels should be kept in storage such as the Data Format Converter (DFC) and the Delay Control Unit (DCU) until they are used. When the size of input image is $N{\times}N$ and m is the filter length, the required storage for the proposed architecture is about 2mN. Since the proposed architecture processes the 2D DWT in horizontal and vertical directions at the same time with 4 input data, the total period for 2D DWT is $N^2(1-2^{-2J})/3$.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.515-518
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• 2000

디지털 워터마킹(Digital Watermarking)은 디지털 미디어 창작물에 대해 불법적인 사용과 인위적인 조작으로부터 소유권과 저작권을 보호하기 위하여 입증 가능한 정보(워터마크)를 사람이 인지하지 못하도록 삽입하는 기술이다. 본 논문에서는 JPEG 2000에서 지원하는 Daubechies 9/7 필터를 이용한 lifting 기반의 DWT(Discrete Wavelet Transform) 중간에 임의의 파라메터를 추가한 lifting 단계를 구성하여 이 부분에 워터마크를 삽입한 후, 다양한 신호처리 왜곡을 가하여 제안한 방법의 성능을 평가하였다. 실험은 8-bit 512×512크기의 영상을 사용하였으며, 무작위로 발생시킨 1과-1을 워터마크 신호로 하여 DWT 시 추가한 lifting 단계에서의 임의의 파라메터 값과 워터마크를 삽입할 각 웨이블릿 변환의 해상도 레벨을 조절해 가면서 선택한 웨이블릿 계수값에 무작위로 발생시킨 워터마크 신호를 삽입하였다. 실험 결과 영상의 일반적인 변형(압축, 필터링 등)에 대해서 제안한 방법의 워터마킹 기법의 성능이 전반적으로 강인함을 확인하였다.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.282-285
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• 2000

Three representations are known to implement the discrete wavelet transform (DWT) ; i.e., direct, lifting and matrix forms. In these representations, direct and lifting forms are well known so far. This paper derives the matrix form of the DWT from the direct form. Then, we implement these three representations on a programmable digital signal processor (in the following, DSP processor) and compare them in terms of the number of calculations and instruction cycles. As a result, we confirm that the lifting form has the lowest number of calculations and cycles, and the matrix form has an effective decrease in the number of cycles than other representations on the DSP processor.