• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.632-634
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• 2004

First for high-qualify images and reducing process-error and driving speed, the designed 8-bit data driving circuit consists of a constant transconductance bias circuit, D-F/Fs by shift registers using static transmission gates, 1st latch and 2nd latch by tristate inverters, level shifters, current steering segmented D/A converters by 4MSB thermometer decoder and 4LSB weighted type. Second, we designed gray amp for power saving. These data driving circuits are designed with $0.35-{\mu}m$ CMOS technologies at 3.3 V and 18 V power supplies and simulated with HSPICE.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.571-575
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• 2017

This paper presents a C-band bi-directional T/R chipset in $0.13{\mu}m$ TSMC CMOS technology for phased array antenna. The T/R chipset, which is a key component of phased array antenna, consists of a 6 bit phase shifter, a 6 bit step attenuator, and three bi-directional gain amplifiers. The phase shifter is controlled up to $354^{\circ}$ with $5.625^{\circ}$ phase step for precise beam steering. The step attenuator is also controlled up to 31.5 dB with 0.5 dB attenuation step for the side lobe level rejection. The LDO(Low Drop Output) regulator for stable 1.2 V DC power and the SPI(Serial Peripheral Interface) for digital control are integrated in the chipset. The chip size is $2.5{\times}1.5mm^2$ including pads.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.7-13
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• 2001

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently. IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. This paper presents a new BIC for the internal current test in CMOS logic circuit. Our circuit is composed of Magnetoresistive current sensor, level shifter, comparator, reference voltage circuit and a circuit be IDDQ tested as a kind of self-testing fashion by using the proposed BIC.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.999-1002
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• 2004

We propose and simulate a new integrated DAC analog buffer composed of only p-type poly-Si TFTs in AMLCD and AMOLED. Proposed circuit employs a voltage level shifter which $V_{OUT}$ has a linear functional relation to $V_{IN}$. The proposed scheme enables to allow a constant $V_{GS}$ of buffer transistor so that the charging speed of pixel data address is improved.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.833-836
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• 2007

A low power and small area source driver using LTPS TFTs is proposed for mobile applications. This source driver adopts level shifter with holding latch function and new R-to-R type digital-to-analog converter (DAC). The power consumption and layout area of the proposed source driver are reduced by 23% and 25% for 16M colors and qVGA AM-OLED panel, respectively.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.487-488
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• 2015

New inverter motor drive systems consume 30%~50% less energy compared to existing motor drive systems. For inverter motor drive systems, the development of a 1200V high side driver is critical. This paper presents an advanced 1200V high side driver with low power consumption and high ruggedness. This solution implements a high voltage level shifter which consumes low power by adding a clamped VGS LDMOS driver to the conventional short pulse generator. Moreover, this paper proposes a highly rugged 1200V LDMOS which improves SOA by limiting the hole current. This paper could be applied to smart power modules used for HVAC (heating, ventilation, and airconditioning) and industrial inverters. Consequently, this paper will provide design engineers with an understanding of how they can make a significant contribution to worldwide energy savings.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.891-901
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• 2003

This paper presents low-power asynchronous barrel shifters for variable length encoders and decoders useful in portable applications using multimedia standards. Our approach is to create multi-level asynchronous barrel shifters optimized for the skewed shift control statistics often found in these codecs. For common shifts, data passes through one level, whereas for rare shifts, data passes though multiple levels. We compare our optimized designs with the straightforward asynchronous and synchronous designs. Both pre- and Post-layout HSPICE simulation results indicate that, compared to their synchronous counterparts, our designs provide over a 40% savings in average energy consumption for a given average performance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.10
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• pp.1252-1262
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• 1988

This paper describes a functional-level design and simulation of Graphics Processor(GP) which can be used in various graphics systems. GP is divided into two parts: One is CPU, and the other is the interface to I/O peripherals. In order to achieve fast execution of graphics instructions, the CPU has special ALU, barrel shifter and window comparator and a FIFO for instruction prefetch. I/O part controls the DRAM and VRAM which constitute the GP's local memory, generates the signals to drive monitor, and communicates with the host processor. The functional simulation of CPU was done on Daisy workstation while the I/O part was designed using GENESIL, a silicon compiler.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.4
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• pp.105-109
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• 2018

In this paper, the performance enhancement of a time-modulated array is described. The proposed time-modulated array is based on the topology of a conventional array but uses apodized discrete time switching, instead of phase shifters, to achieve beamforming functions with side-band suppression. Numerical simulations are carried out to examine the performance of this beamforming system based on apodized time sequence of 16 elements linear array. Numerical results reveal that the proposed method provides a more flexible and accurate way of producing desired beampatterns with low or ultralow side-lobe level (SLL) compared with the conventional methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.93-100
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• 2009

This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.