• 제목/요약/키워드: Leakage current elimination

검색결과 12건 처리시간 0.023초

오프셋 마스크를 이용하지 않는 새로운 자기 정합 폴리 실리콘 박막 트랜지스터 (A novel self-aligned offset gated polysilicon thin film transistor without an additional offset mask)

  • 민병혁;박철민;한민구
    • 전자공학회논문지A
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    • 제32A권5호
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    • pp.54-59
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    • 1995
  • We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.

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A Study on a Carrier Based PWM having Constant Common Mode Voltage and Minimized Switching Frequency in Three-level Inverter

  • Ahn, Kang-Soon;Choi, Nam-Sup;Lee, Eun-Chul;Kim, Hee-Jun
    • Journal of Electrical Engineering and Technology
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    • 제11권2호
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    • pp.393-404
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    • 2016
  • In this paper, a carrier-based pulse with modulation (PWM) strategy for three-phase three-level inverter is dealt with, which can keep the common mode voltage constant with minimized switching frequency. The voltage gain and the switching frequency in overall operating ranges including overmodulation are investigated and the analytic equations are presented. Finally, the leakage current reduction effect is confirmed by carrying out simulation and experiment. It will be pointed out that the leakage current cannot be perfectly eliminated because of the dead time.

Design of a 25 mW 16 frame/s 10-bit Low Power CMOS Image Sensor for Mobile Appliances

  • Kim, Dae-Yun;Song, Min-Kyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제11권2호
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    • pp.104-110
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    • 2011
  • A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

Harmonic Elimination and Reactive Power Compensation with a Novel Control Algorithm based Active Power Filter

  • Garanayak, Priyabrat;Panda, Gayadhar
    • Journal of Power Electronics
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    • 제15권6호
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    • pp.1619-1627
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    • 2015
  • This paper presents a power system harmonic elimination using the mixed adaptive linear neural network and variable step-size leaky least mean square (ADALINE-VSSLLMS) control algorithm based active power filter (APF). The weight vector of ADALINE along with the variable step-size parameter and leakage coefficient of the VSSLLMS algorithm are automatically adjusted to eliminate harmonics from the distorted load current. For all iteration, the VSSLLMS algorithm selects a new rate of convergence for searching and runs the computations. The adopted shunt-hybrid APF (SHAPF) consists of an APF and a series of 7th tuned passive filter connected to each phase. The performance of the proposed ADALINE-VSSLLMS control algorithm employed for SHAPF is analyzed through a simulation in a MATLAB/Simulink environment. Experimental results of a real-time prototype validate the efficacy of the proposed control algorithm.

공간전압벡터 PWM을 이용한 컨버터/인버터 시스템에서의 커먼 모드 전압 펄스 제거 (Elimination of a Common Mode Voltage Pulse in Converter/Inverter System Modifying Space-Vector PWM Method)

  • 이현동;이영민;설승기
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제48권2호
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    • pp.89-96
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    • 1999
  • This paper proposes a common-mode voltage reduction method base on SVPWM(Space-Vector Pulsewidth Modulation) in three phase PWM converter/inverter system. By shifting the active voltage vector of inverter and aligning this to the active vector of converter, it is possible to eliminate a common-mode voltage pulse in one control period. Since the proposed PWM method maintains the active voltage vector, it does not affect the control performance of PWM converter/inverter system. Without any extra hardware, overall common mode voltage dv/dt and conrresponding leakage current can be reduced to two-third of the conventional three phase symmetric SVPWM scheme.

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트랜치 기법을 이용한 SOI MOSFET의 전기적인 특성에 관한 연구 (A New Structure of SOI MOSFETs Using Trench Mrthod)

  • 박윤식
    • 한국컴퓨터산업교육학회:학술대회논문집
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    • 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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    • pp.67-70
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    • 2003
  • In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

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PDP 유지전원단을 위한 높은 효율을 갖는 새로운 페이지쉬프트 풀브릿지 컨버터 (A New High Efficiency Phase Shifted Full Bridge Converter for Sustaining Power Module of Plasma Display Panel)

  • 이우진;김정은;한상규;문건우
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2005년도 전력전자학술대회 논문집
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    • pp.445-448
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    • 2005
  • PDP 유지전원단을 위한 고효율을 갖는 새로운 페이지 쉬프트 풀브릿지 컨버터를 제안한다. 제안된 컨버터는 Rectifier로 Voltage Doubler를 사용함으로서, 큰 사이즈의 Output Inductor가 없게 되어 간단한 구조를 가지게 되며 Rectifier Diodes의 전압 스트레스가 출력전압으로 클램핑되어서 스너버회로가 필요없다는 장점을 가지게 된다. 또한 넓은 영전압 스위칭 구간을 가지며, 트랜스포머의 기생성분인 Leakage 인덕터와 Voltage doubler의 캐패시터간의 공진을 이용함으로서 전류가 작은 RMS값을 가지게 되어서 낮은 도통손실과 Rectifier Diode의 전류 스트레스 또한 낮다는 장점을 가지게 된다. 본 논문을 통해 제안된 컨버터의 동작원리와 해석, 실험을 수행하였다.

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A New High Efficiency Phase Shifted Full Bridge Converter for a Power Sustaining Module of Plasma Display Panel

  • Lee Woo-Jin;Kim Chong-Eun;Han Sang-Kyoo;Moon Gun-Woo
    • Journal of Power Electronics
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    • 제6권1호
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    • pp.45-51
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    • 2006
  • A new high efficiency phase shifted full bridge (PSFB) converter for the power sustaining module of a plasma display panel (PDP) is proposed in this paper. The proposed converter employs a voltage doubler rectifier without an output inductor. Since it has no output inductor, the voltage stresses of the secondary rectifier diodes can be clamped at the output voltage level. No dissipative resistor-capacitor (RC) snubber for rectifier diodes is needed. Therefore, high efficiency, as well as, a low noise output voltage can be realized. Due to the elimination of the large output inductor, it features a simple structure, lower cost, smaller mass and lighter weight. Furthermore, the proposed converter has wide zero voltage switching (ZVS) ranges with low current stresses of the primary switches. Also the resonance between the leakage inductor of the transformer and the capacitor of the voltage doubler cell reduces the current stresses of the rectifier diodes. In this paper, operational principles, an analysis of the proposed converter and experimental results are presented.

완전차폐 및 이온조절형 연X선식 정전기제거장치의 개발 (Development of Radiation Free Soft X-Ray Ionizer with Ion Control)

  • 정필훈;이동훈
    • 한국안전학회지
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    • 제31권5호
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    • pp.22-27
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    • 2016
  • The Electrostatic Charge Prevention Technology is a core factor that highly influences the yield of Ultra High Resolution Flat Panel Display and high-integrated semiconductor manufacturing processes. The corona or x-ray ionizations are commonly used in order to eliminate static charges during manufacturing processes. To develop such a revolutionary x-ray ionizer that is free of x-ray radiation and has function to control the volume of ion formation simultaneously is a goal of this research and it absolutely overcomes the current risks of x-ray ionization. Under the International Commission on Radiological Protection, it must have a leakage radiation level that should be lower than a recommended level that is $1{\mu}Sv/hour$. In this research, the new generation of x-ray ionizer can easily control both the volume of ion formation and the leakage radiation level at the same time. In the research, the test constraints were set and the descriptions are as below; First, In order not to leak x-ray radiation while testing, the shielding box was fully installed around the test equipment area. Second, Implement the metallic Ring Electrode along a tube window and applied zero to ${\pm}8kV$ with respect to manage the positive and negative ions formation. Lastly, the ion duty ratio was able to be controlled in different test set-ups along with a free x-ray leakage through the metallic Ring Electrode. In the result of experiment, the maximum x-ray radiation leakage was $0.2{\mu}Sv/h$. These outcome is lower than the ICRP 103 recommended value, which is $1{\mu}Sv/h$. When applying voltage to the metallic ring electrode, the positive decay time was 2.18s at the distance of 300 mm and its slope was 0.272. In addition, the negative decay time was 2.1s at the distance of 300 mm and its slope was 0.262. At the distance of 200 mm, the positive decay time was 2.29s and its slope was 0.286. The negative decay time was 2.35s and its slope was 0.293. At the distance of 100 mm, the positive decay time was 2.71s and its slope was 0.338. The negative decay time was 3.07s and its slope was 0.383. According to these research, the observation was shown that these new concept of ionizer is able to minimize the leakage radiation level and to control the positive and negative ion duty ratio while ionization.

유한요소법에 의한 변압기의 자속분포 해석에 관한 연구 (Study on the magnetic flux distribution of transformer by the use of finite element method)

  • 임달호;현동석;이철직
    • 전기의세계
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    • 제29권4호
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    • pp.247-255
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    • 1980
  • In this study, an application of Finite Element Method which, in principle, based on variational calculus has been presented for the two-dimensional analysis of magnetic flux distribution in the shell type core of single phase transformer. The necessary stationarity condition of energy functional and boundary conditions were determined under the assumptions that the electromagnetic field considered is stationary and that the effect of eddy current is negligible. In the process of application the domain of magnetic field was divided into triangle subsectional elements and then the matrix equations were constructed for the respective triangular element and for those of all after the manipulation of minimization process to the vector potential of magnetic field at the each vertex of the element. Furthermore the numerical computation for the equations was guided by the Gaussian Elimination Methods. As the results obtained, it is found that the aspect of magnetic flux distribution inside the core as well as the leakage flux profile at the vicinity of the inner leg of the core is not much different from the well-known distribution profile of magnetic flux, however, the procedure shows to possess the merit of the uniquely deterministic nature for the flux distribution at the desired points.

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