• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.176-182
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• 1992

t-Stress and junction leakage current characteristics of CVD-tungsten have been investigated. Stressversus continuous annealing temperature plot. shows hysteresis curve where the stress level of the cooling curveis higher than that of the heating curve. It is found that the thermal and intrinsic stress of tungsten film depositedby SiH4 reduction is higher than that by Hz reduction.The tungsten film deposited by SiHl reduction is in the tensile stress state below 700"Cnd the stress ofthe film decreses with increasing annealing temperature. The stress state changes into compressive stress atabout 700"Cnd the compressive stress increases rapidly with increasing temperature.Leakage current of the n+/p diode increases rapidly especially in the range of 400-450$^{\circ}$C with increasingdeposition temperature of the CVD-W by SiH4 reduction, which is due to the Si consumption by W encroachment.On the other hand leakage current of the n+/p diode slightly increases with increasing SiH4/WF6 ratio.h increasing SiH4/WF6 ratio.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.7
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• pp.891-897
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• 2013

The power system frequency plays an important role in monitoring and controlling the power system. The frequency can be measured through discrete Fourier transform (DFT) coefficients of its positive fundamental frequency. The accuracy of the frequency estimate is severely affected by noise in the power system signal and the leakage effect of the negative fundamental frequency in DFT. This paper proposes a DFT-based frequency estimation algorithm to cope with the noise as well as the leakage effect. In this algorithm, two suitable digital filters are introduced to reduce efficiently frequency estimate error due to the noise. These filters are designed to use a digital bandpass filter and a second-degree integrator. The effectiveness of the proposed algorithm in reduction of frequency estimate error is verified through simulations on noise, harmonics and frequency deviation.

• ETRI Journal
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• v.13 no.2
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• pp.21-27
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• 1991

Effects of annealing on the dielectric properties and microstructures of thin tantalum oxide film(25nm) deposited on p-type Si substrate with rf reactive magnetron sputtering were investigated. The leakage current density was remarkably reduced from $10^-8$ to $10^-12$ A/$\mum^2$at the electric field of 2MV/cm after rapid thermal annealing(RTA) in $O_2$at $1000^{\circ}C$, while little leakage reduction was observed after furnace annealing in $O_2$ at $500^{\circ}C$. The structural changes of thin tantalum oxide film after annealing were examined using high resolution electron microscope(HREM). The results of HREM show that substantial reduction in the leakage current density after the RTA in $O_2$ can be attributed to crystallization and reoxidation of the thin amorphous tantalum oxide film.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.5
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• pp.446-454
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• 2022

This study proposes a carrier-based pulse width modulation (PWM) method for leakage current reduction and neutral point (NP) current control in a three-phase three-level converter, which is a carrier-based PWM version of the previously proposed low-frequency common mode voltage PWM. Three groups of space vectors with the same common mode voltage are used. When the averaged NP current needs to be positive or negative, the specific groups are employed to produce low-frequency common mode voltages. The validity of the proposed PWM method is verified through experiments.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.918-923
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• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1250-1252
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• 1993

Enhancement mode n-channel TFT leakage current(off current : $V_G<0$) that is little agreement on the conduction mechanism is major disadvantage of poly-silicon TFT in practical use, characteristic analysis and model ing. In this paper, new modeling of leakage current is proposed. The activation energy of leakage current, which is dependent on gate voltage, and leakage current dependent on poly silicon thickness are plausibly explained with this model. This model indicate that the reduction of leakage current is attributable to a decrease of maximum laterial electric field strength in the drain depletion region and to the density of trap.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1321-1323
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• 1998

We investigated drain leakage current in GaAs power MESFET. The device we studied by 20 simulation has a $1000{\AA}$ thick AlGaAs buffer layer under n-GaAs active layer. The calculation shows that the leakage current through GaAs substrate is significantly reduced by the buffer layer.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2008.03a
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• pp.160-167
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• 2008

The effects of squealer rim height on three-dimensional flows and aerodynamic losses downstream of a high-turning turbine rotor blade have been investigated for a typical tip gap-to-chord ratio of h/c=2.0%. The squealer rim height-to-chord ratio is changed to be $h_{st}/c$=0.00(plane tip), 1.37, 2.75, 5.51, and 8.26%. Results show that as $h_{st}/c$ increases, the tip leakage vortex tends to be weakened and the interaction between the tip leakage vortex and the passage vortex becomes less severe. The squealer rim height plays an important role in the reduction of aerodynamic loss when $h_{st}/c{\leq}2.75%$. In the case of $h_{st}/c{\geq}5.51%$, higher squealer rim cannot provide an effective reduction in aerodynamic loss. The aerodynamic loss reduction by increasing $h_{st}/c$ is limited only to the near-tip region within a quarter of the span from the casing wall.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.6
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• pp.469-475
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• 2017

Using impedance matching techniques as a way to increase system power transferability in capacitive wireless power transmission has been widely investigated in conventional studies. However, these techniques tend to increase the circuit volume and thus counterbalance the advantage of the simplicity in the energy link structure. In this paper, a compact circuit topology with one leakage-enhanced transformer is proposed in order to minimize the circuit volume for the capacitive power transfer system. This topology achieves a reactive compensation, and the system quality factor value can be reduced by the turn ratio. As a result, this topology not only reduces the overall system volume but also minimizes the voltage stress of the link capacitor. An optimal design guideline for the leakage-enhanced transformer is also presented. The advantages of the proposed scheme over the conventional method in terms of power efficiency and circuit volume are revealed through an analytic comparison. The feasibility of applying the new topology is also verified by conducting 50 W hardware tests.