• JSTS:Journal of Semiconductor Technology and Science
• /
• v.2 no.4
• /
• pp.273-279
• /
• 2002

This paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electro-chemical etch-stop for the protection of circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with $p^{++}$ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have $3{\;}\mu\textrm{m}$ thick suspension beams and $15{\;}\mu\textrm{m}$ thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2003.07a
• /
• pp.1005-1008
• /
• 2003

We report a new FCOG (flip chip on glass) technique using solder bumps for display packaging applications. The In and Sn solder bumps of 40 ${\mu}m$ pitches were formed on Si and glass substrate. The In and Sn bumps were bonded at 125 at the pressure of 3 mN/bump. The metallurgical bonding was confirmed using cross-sectional SEM. The contact resistance of the solder joint was 65 $m{\Omega}$ which was much lower than that of the joint made using the conventional ACF bonding technique. We demonstrate that the new COG technique using solder bump to bump direct bonding can be applied to advanced LCDs that lead to require higher quality, better resolution, and lower power consumption.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.18 no.12
• /
• pp.3195-3201
• /
• 1994

In order to analytically predict tapping torque and thrust force in high speed tapping, a cutting model for main cutting edge with a uniformly restricted tool-chip contact area were developed. From this model equations are derived for the prediction of tapping torque given the cutting conditions, tap geometry, and an empirical factor which is related to the workmaterial. Computed values of torque is shown to compare favorably with those obtained from tapping tests on 16MnCr5. The applied torque about the cutting edge of teeth at lead chamfer is estimated respectively and it is shown that observed value is gradually decreased with following teeth.

• Journal of Welding and Joining
• /
• v.35 no.3
• /
• pp.7-14
• /
• 2017

The effect of high temperature-moisture on corrosion and mechanical properties for Sn-0.7Cu, Sn-3.0Ag-0.5Cu (SAC305) solders on flexible substrate was studied using Highly Accelerated Temperature/Humidity Stress Test (HAST) followed by three-point bending test. Both Sn-0.7Cu and SAC305 solders produced the internal $SnO_2$ oxides. Corrosion occurred between the solder and water film near flexible circuit board/copper component. For the SAC305 solder with Ag content, furthermore, octahedral corrosion products were formed near Ag3Sn. For the SAC305 and Sn-0.7Cu solders, the amount of internal oxide increased with the HAST time and the amount of internal oxides was mostly constant regardless of Ag content. The size of the internal oxide was larger for the Sn-0.7Cu solder. Despite of different size of the internal oxide, the fracture time during three-point bending test was not significantly changed. It was because the bending crack was always initiated from the three-point corner of the chip. However, the crack propagation depended on the oxides between the flexible circuit board and the Cu chip. The fracture time of the three-point bending test was dependent more on the crack initiation than on the crack propagation.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.124-130
• /
• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2001.11a
• /
• pp.111-114
• /
• 2001

Optical transmitter and receiver are the essential components for optical communication. For these components, butterfly type packages are used which are comprised of metal housing, multilayer ceramic inserts, lead and window. In this study, 2.5 Gbps DFB(Distributed -Feedback) LD(Laser Diode) package was fabricated and characterized. Metal housing showed good thermal conductivity (200W/mK) and well matched TCE(6.7ppm/K) with GaAs chip. Ceramic inserts also showed good VSWR(Voltage Standing Wave Ratio) characteristics(<2.0). By brazing technology, all the elements were combined and sealed. RF characteristics of the package mounted on the PWB was also tested.

• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.1978.1_1979.1
• /
• 2009

In this paper, we have proposed and demonstrated a tonometry sensor array for measuring arterial pulse pressure. A sensor module consists of 7 piezoresistive pressure sensor array. Wire-bonded connection was provided between silicon chip and lead frame. PDMS(poly-dimethylsiloxane) was coated on the sensor array to protect fragile sensor while faithfully transmitting the pressure of radial artery to the sensor. Tonometric pulse pressure can be measured by this packaged sensor array that provides the pressure value versus the output voltage.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.4
• /
• pp.83-89
• /
• 2014

Solder paste plays a crucial role as the widely used joining material in surface mount technology (SMT). The understanding of its behaviour and properties is essential to ensure the proper functioning of the electronic assemblies. The composition of the solder paste is known to be directly related to its rheological behaviour. This paper provides a brief overview of the solder paste behaviour of four different solder paste formulations, stencil printing processes, and techniques to characterize solder paste behaviour adequately. The solder pastes are based on the Sn-3.0Ag-0.5Cu alloy, are different in their particle size, metal content and flux system. The solder pastes are characterized in terms of solder particle size and shape as well as the rheological characterizations such as oscillatory sweep tests, viscosity, and creep recovery behaviour of pastes.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.4
• /
• pp.61-70
• /
• 1998

The electrical performance of a package is extremely important for high speed digital system operations. CSP(chip scale package) is known to have better electrical performance than the convnetional packages. In this paper, the electrical performance of the BLP(bottom leaded plastic) package, a kind of CSP, has been alayzed by both simulation and real measurement. The electrical perfdormance of a BLP was compared with that of the conventioanl TSOP(thin small outline package). The leadinductanceand lead capacitance were used for the comparison purposes. The new BLP design provides much better electrical performance that TSOP package. It has about 40% favorable parameter values.

• Journal of Institute of Control, Robotics and Systems
• /
• v.16 no.2
• /
• pp.172-176
• /
• 2010

Recently, LCD (Liquid Crystal Display) requires various technical challenges; high definition, high quality, big size, and low price. These demands more pixels in the fixed area of the LCD and very fine lead pitch of the driving IC which controls the pixels. Therefore, a new packaging technology is needed to meet such technical requirement. NCP (Non Conductive Paste) is one of the new packaging methods and has excellent characteristics to overcome the problems of the ACF (Anisotropic Conductive Film). In this paper, we analyzed the process of the NCP for COF (Chip on FPCB) and proposed the key design parameters of the NCP process. Through a series of experiments, we obtained the stable values of the design parameters for successful NCP process.