• Journal of Institute of Control, Robotics and Systems
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• v.5 no.6
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• pp.698-704
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• 1999

There are several types of defects of SMDs mounted on PCB, that is, missing components, misalignment, wrong parts and poor solder joints. This research study mainly focuses on measuring of deviation of SMD leads using the partial image of component, not using the full image. This processing based on the partial image has the advantage of the reduction in calculation time compared to the full image. Since position of lead is calculated with respect of the reduction in calculation time compared to the full image. Since position of lead is calculated with respect to pad, the accuracy of the system is not dependent on percise positioning stage. The grabbed image of gray scale is converted into binary format using a cutomatic threshold. After small fragments in the image is removed by a series of morphology operations such as opening and closing, the centroids of PCB pads and SMD leads is obtained together with labeling of blobs. Translational shift and rotationial angle of SMD are succedingly estimated using above information and chip data. The expression that can calculate the maximum deviation of leads with respect to PCB pads has been derived, and inferior mounting of SMD is judged by a given criterion. Some experiments have been executed to verify this measuring scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.2
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• pp.107-119
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• 1988

An 8-channel digital filter bank with wave digital filters(WDF) is studied. Wave digital filtwr is automatically a directional filter. Using these properties, a new method for organizing the 8-channel digital filter bank is proposed. This will lead to enormous savings in memories for the digital signal processign chip.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.34-41
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• 2001

Semiconductors performing digital clocking are a main source of radiated emission noise. Therefore, the most secure method of reducing emission noise is to reduce emission radiated from semiconductors; an application of an absorber to the surface of semiconductors is one of these methods, too. However, in reality, it is difficult to achieve as much effect of noise reduction as expected by using only absorber. It is confirmed by experiment in this paper that a loop area within chip has no correlation with radiated emission noise and it is clarified why the existing absorber fails to achieve a satisfactory effect of emission noise reduction. Besides, a new type of chip coating absorber has been developed which can cover up to semiconductor out lead by using ferrite coating material of ferrite/epoxy acrylate substance using only permeability loss out of electromagnetic wave reduction characteristics of materials. As a result of evaluating radiated emission noise by applying this coating absorber to semiconductor device, it could be confirmed that emission noise decreased from about 3 ㏈ up to 20㏈ depending on frequency.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.2
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• pp.162-172
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• 1991

In proportion to the capacity enlargement of the induction motor system controlled by current source inverter, the capacitance of the commutating capacitor is enlarged and then the spike value of output voltage is increased at the moment of charge and discharge. Moreover, the output currnet includes a number of harmonic components. Such voltage spike and harmonics generate the torque ripple and lead to bad effects on the performance of the induction motor. In this study, all the harmonics excluding 17th and 19th harmonics were mostly elimunated by adopting 18-phase Triple High Frequency Current Source Inverter(HFCSI), and the spike component of output voltage was reduced by adding the Voltage Clamping Circuit(VCC). As a result, the torque ripple and the commutation loss were reduced and the performance of the system was improved. Experiments for speed control were carried out in the tripple current source inverter system for induction motor drive. Overall system was controlled by ONE CHIP MICROCOMPUTER(INTEL 8751). Control circuits were simplified and good experimental results in the constant V/F control were obtained due to the flexibility of the microcomputer.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.1-4
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• 2009

This work shows how the adoption of a dual-dicing process for silicon wafer separation affects the thermal-cycling reliability (i.e. $-65^{\circ}C$ to $150^{\circ}C$) of the semiconductor devices utilizing lead-on-chip (LOC) die attach technique. In-situ examinations show that conventional single-dicing process directly attacks the edge region of diced devices but dual-dicing process effectively protects the edge region of diced devices from dicing-induced mechanical damage. Probably, this is because the preferential and sacrificial fracture of notched regions induced on the active surface of wafers saves the edge regions. It was also investigated through thermal-cycling tests that the number of thermal-cycling induced failures is much lower at the dual-dicing process than the single-dicing process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.8
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• pp.3301-3306
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• 2012

In LED chip packaging, die bonding is a very important process which fixes the LED chip on the lead frame to provide enough strength for the next process. Conventional pick-up device of the die bonder is simply operated by up and down motion of a collet and an ejector pin. However, this method may cause undesired problems such as position misalignment and/or severe die damage when the pick-up device reaches the die. In this study, to minimize the position alignment error and die damage, a die bonder is developed by adopting a new pick-up head for precise alignment and high speed feeding. To evaluate structural stability of the designed system, required finite element model of the die bonder is generated, and structural analysis is performed. Vibration analysis of the pick-up head is also performed using developed finite element model at operation frequency range. As a result of the analysis, deformation, stress, and natural frequency of the die bonder are investigated.

• Journal of radiological science and technology
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• v.42 no.5
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• pp.379-385
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• 2019

Radiation is used for various purposes such as cancer therapy, research of industrial and drugs. However, in case of radiation accidents such as terrorism, collapsing nuclear plant by natural disasters like Fukushima in 2011, very high radiation does expose to human and could lead to death. For this reason, many people are concerning about radiation exposures. Therefore, assessment and research of retrospective radiation dose to human by various path is an necessary task to be continuously developed. Radiation exposure for workers in radiation fields can be generally measured using a personal exposure dosimeter such as TLD, OSLD. However, general people can't be measured radiation doses when they are exposed to radiation. And even if radiation fields workers, when they do not in possession personal dosimeter, they also can't be measured exposure dose immediately. In this study, we conduct retrospective research on reconstruction of dose after exposure by using smart chip card of personal items through Optically Stimulated Luminescence (OSL). The OSL signal of smart chip card shows linear response from 0.06 Gy to 15 Gy and results of fading rate 45 %, 48% for 24 and 48 hours due to the natural emission of radiation in sample, respectively. The minimum detectable limit (MDD) was 0.38 mGy. This values are expected to use as correction values for reconstruction of exposure dose.

• BioChip Journal
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• v.12 no.4
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• pp.304-308
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• 2018

Atopic disease is caused by a complex combination of environmental factors and genetic factors, and studies on influence of exposure to various environmental factors on atopic diseases are continuously reported. However, the exact cause of atopic dermatitis is not yet known. Our study was conducted to analyse the association of SNPs with the development of atopic disease in a small cohort. Samples were collected from the Mothers' and Children's Environmental Health (MOCEH) study and 192 cord blood DNA samples were used to identify incidence of atopy due to influence of exposure to environmental factors. Genetic elements were analysed using a precision medicine research (PMR) array designed with various SNPs for personalized medicine. Case-control analysis of atopy disease revealed 253 significant variants (p<0.0001) and SNPs on five genes (CARD11, ZNF365, KIF3A, DMRTA1, and SFMBT1) were variants identified in previous atopic studies. These results are important to confirm the genetic mutation that may lead to the onset of foetal atopy due to maternal exposure to harmful environmental factors. Our results also suggest that a small-scale genome-wide association analysis is beneficial to confirm specific variants as direct factors in the development of atopy.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.140-143
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• 2004

Chemical mechanical polishing(CMP) is essential technology to secure the depth of focus through the global planarization of wafer. But a variety of defects such as contamination, scratch, dishing, erosion and corrosion are occurred during CMP. Especially, dishing and erosion defects increase the resistance because they decrease the interconnect section area, and ultimately reduce the life time of the semiconductor. Due to this dishing and erosion must be prohibited. The pattern density and size in chip have a significant influence on dishing and erosion occurred over-polishing. Decreasing of abrasive concentration results in advanced pattern selectivity which can lead the uniform removal in chip and decrease of over-polishing. The fixed abrasive pad was applied and tested to reduce dishing and erosion in this paper. Consequently, reduced dishing and erosion was observed in CMP of tungsten pattern wafer with proposed fixed abrasive pad and chemicals.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.2
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• pp.38-45
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• 2005

Chemical mechanical polishing(CMP) has been widely accepted for the planarization of multi-layer structures in semiconductor fabrication. But a variety of defects such as abrasive contamination, scratch, dishing, erosion and corrosion are occurred during CMP. Especially, dishing and erosion defects increase the metal resistance because they decrease the interconnect section area, and ultimately reduce the lift time of the semiconductor. Due to this reason dishing and erosion must be prohibited. The pattern density and size in chip have a significant influence on dishing and erosion occurred by over-polishing. The fixed abrasive pad(FAP) was applied and tested to reduce dishing and erosion in this paper. The abrasive concentration decrease of FAP results in advanced pattern selectivity which can lead the uniform removal in chip and declining over-polishing. Consequently, reduced dishing and erosion was observed in CMP of tungsten pattern wafer with proposed FAP and chemicals.