• 한국결정성장학회지
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• 제12권6호
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• pp.304-310
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• 2002

실리콘 기판 위의 초기 산화막을 NO 열처리 및 재산화 공정방법으로 성장한 재산화된 질화산화막을 게이트 유전막으로 사용한 새로운 전하트랠형 기억소자로의 응용가능성과 계면트랩특성을 조사하였다. 0.35$\mu$m CMOS 공정기술을 사용하여 게이트 유전막은 초기산화막을 $800^{\circ}C$에서 습식 산화하였다 전하트랩영역인 질화막 층을 형성하기 위해 $800^{\circ}C$에서 30분간 NO 열처리를 한 후 터널 산화막을 만들기 위해 $850^{\circ}C$에서 습식 산화방법으로 재산화하였다. 프로그램은 11 V, 500$\mu$s으로 소거는 -l3 V, 1 ms의 조건에서 프로그래밍이 가능하였으며, 최대 기억창은 2.28 V이었다. 또한 11 V, 1 ms와 -l3 V, 1 ms로 프로그램과 소거시 각각 20년 이상과 28시간의 기억유지특성을 보였으며 $3 \times 10^3$회 정도의 전기적 내구성을 나타내었다. 단일접합 전하펌핑 방법으로 소자의 계면트랩 밀도와 기억트랩 밀도의 공간적 분포를 구하였다. 초기상태에서 채널 중심 부근의 계면트랩 및 기억트랩 밀도는 각각 $4.5 \times 10^{10}/{cm}^2$ 와 $3.7\times 10^{1R}/{cm}^3$ 이었다. $1 \times 10^3$프로그램/소거 반복 후, 계면트랩은 $2.3\times 10^{12}/{cm}^2$으로 증가하였으며, 기억트랩에 기억된 전하량은 감소하였다.

• 한국결정성장학회지
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• 제11권1호
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• pp.38-42
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• 2001

Electric and dielectric(Ba,Sr)$TiO_3$[BST] thin films for emtal-Insulator-Semiconductor(MIS) capacitors have been studied. BST thin films wre deposted on p-Si(100) substrates bythe RF magnetron sputtering with tempratue range of 500~$600^{\circ}C$. The dielectric properties of MIS capacitors consisting of Al/BST/$SiO_2$/Si sandwich structure were evaluated ot redcue the leakage current density. The charge state densities of the MIS capacitors were determined by high frequency (1 MHz) C-V measurement. In order to reduce the leakage current in MIS capacitor, high quality $SiO_2$ layer was deposited on bare p-Si substrate. Depending on the oxygen pressure and substrate temperature both positive and negative polarities of effective oxide charge in the MIS capacitors were evaluated. It is considered that the density of electronic states, generated at the BST/$SiO_2$/p-Si interface due to the asymmetric structure within BST/$SiO_2$/Si structure, and the oxygen vacancy content has influence on the behavior of oxide charge.

• 반도체디스플레이기술학회지
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• 제18권2호
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• pp.98-102
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• 2019

Direct plasma-enhanced atomic layer deposition (PEALD) are widely used for $SiO_2$ and SiON thin film process in current semiconductor industry. However, this exhibits poor step coverage for three-dimensional device structure due directionality of plasma species as well as plasma damage on the substrate. In this study, to overcome this issue, low temperature (< $300^{\circ}C$) $SiO_2$ and SiON thin film processes were studied using inductively coupled plasma (ICP) type remote PEALD with various reactant gases such as $O_2$, $H_2O$, $N_2$ and $NH_3$. It was confirmed that the interfacial properties such as fixed charge density and charge trapping behavior of thin films were considerably improved by hydrogen species in $H_2O$ and $NH_3$ plasma compared to the films grown with $O_2$ and $N_2$ plasma. Furthermore, the leakage current density of the thin films was suppressed for same reason.

• Korean Chemical Engineering Research
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• 제50권2호
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• pp.379-384
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• 2012

이산화티탄 표면에 흡착되는 금 입자의 분포 또는 그 반대 경우의 분포에 영향을 끼칠 수도 있는 정전기적 상호작용과 금 입자를 코팅한 Glutathione 층의 표면물성을 규명하였다. 이를 위하여, 원자힘현미경(AFM)으로 Glutathione 층표면과 이산화티탄표면 사이의 표면힘을 염 농도와 pH 값에 따라 측정하였다. 측정된 힘은 Derjaguin-Landau-Verwey-Overbeek(DLVO) 이론으로 해석되어 표면의 정전기적인 특성들이 정량적으로 산출되었다. 이 특성들이 염 농도와 pH에 대하여 나타내는 의존성을 질량보존의 법칙으로 기술하였다. pH 8과 11에서 실험으로 산출된 표면 특성의 염 농도 의존성은 이론적으로 예측했던 결과와 일치하는 것으로 관찰되었다. pH 8과 11에서 Glutathione 층의 표면이 이산화티탄 표면보다 높은 정전기적 특성을 갖는 것이 발견되었는데, 이는 Glutathione 층의 이온화-기능-그룹에 기인한 것으로 생각된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.82-85
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• 1992

In this study, charge pumping method was used to investigate the Si-SiO$_2$interface characteristics of the nonvolatile SNOSFET memory devices, fabricated using the CMOS 1 Mbit processes (1.2$\mu\textrm{m}$ design rule), with thin oxide layer of 30${\AA}$ thick and nitride layer of 525${\AA}$ thick on the n-type silicon substrate (p-channel). Charge pumping current characteristics with the pulse base level were measured for various frequencies, falling times and rising times. By means of the charge dynamics in a non-steady state, the average Si-SiO$_2$interface state density and capture cross section were determined to be 3.565${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ and 4.834${\times}$10$\^$-16/$\textrm{cm}^2$, respectively. However Si-SiO$_2$ interface state densities were disributed 2.8${\times}$10$\^$-11/～5.6${\times}$10$\^$11/cm$\^$-2/～6${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ in the lover half of energy gap.

• 반도체디스플레이기술학회지
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• 제18권4호
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• pp.134-137
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• 2019

In this paper, the data retention characteristics were analyzed to find out the thickness effect on the trap energy distribution of silicon nitride in the silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. The nitride films were prepared by low pressure chemical vapor deposition (LPCVD). The flat band voltage shift in the programmed device was measured at the elevated temperatures to observe the thermal excitation of electrons from the nitride traps in the retention mode. The trap energy distribution was extracted using the charge decay rates and the experimental results show that the portion of the shallow interface trap in the total nitride trap amount including interface and bulk trap increases as the nitride thickness decreases.

• 한국전기전자재료학회논문지
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• 제23권8호
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• pp.638-644
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• 2010

We have carry out numerical simulation of the electric-optical characteristics of organic light emitting diodes with gradient-doped emitting layer which were reported to be effective in improving luminous efficiency and lifetime. In this paper, the basic structure is comprised of ITO/NPB/$Alq_3$:C545T[%]/$Alq_3$/LiF/Al, six devices by separating the emitting layer of $Alq_3$:C545T[%] were studied. As the result, the uniformly-doped devices exhibited superior luminous efficiency-current density characteristics over conventional undoped device. In the case of gradient-doped devices, electric-optical characteristics were improved similar to uniformed-doped devices, unusually the distribution of traped-charge density in the OLED devices was shown as the staircase.

• 마이크로전자및패키징학회지
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• 제22권4호
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• pp.111-115
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• 2015

실리콘 태양전지의 효율을 향상하기 위해서는 소수 캐리어의 높은 수명이 필수조건이다. 따라서, 이를 달성하기 위한 실리콘 표면결함을 없애줄 수 있는 부동화(passivation) 기술이 매우 중요하다. 일반적으로 PECVD 법이나 열산화 공정을 통해 얻어진 $SiO_2$ 박막이 부동화 층으로 많이 사용되나 1000도에 이르는 고온 공정과 낮은 열적 안정성이 문제로 여겨진다. 본 연구에서는 원자층 증착법을 이용하여 400도 미만의 저온 공정을 통해 $Al_2O_3$ 부동화 박막을 형성하였다. $Al_2O_3$ 박막은 고유의 음의 고정 전하밀도로 인해 낮은 표면 재결합속도를 보이는 것으로 알려져 있다. 본 연구에서는 질소 도핑을 통해 높은 음의 고정 전하 밀도를 얻고 이를 통해 좀 더 향상된 실리콘 표면 부동화 특성을 얻고자 하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.581-588
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• 2013

This paper presents a study of the process temperature dependence of $Al_2O_3$ film grown by thermal atomic layer deposition (ALD) as a passivation layer in the crystalline Si (c-Si) solar cells. The deposition rate of $Al_2O_3$ film maintained almost the same until $250^{\circ}C$, but decreased from $300^{\circ}C$. $Al_2O_3$ film deposited at $250^{\circ}C$ was found to have the highest negative fixed oxide charge density ($Q_f$) due to its O-rich condition and low hydroxyl group (-OH) density. After post-metallization annealing (PMA), $Al_2O_3$ film deposited at $250^{\circ}C$ had the lowest slow and fast interface trap density. Actually, $Al_2O_3$ film deposited at $250^{\circ}C$ showed the best passivation effects, that is, the highest excess carrier lifetime (${\tau}_{PCD}$) and lowest surface recombination velocity ($S_{eff}$) than other conditions. Therefore, $Al_2O_3$ film deposited at $250^{\circ}C$ exhibited excellent chemical and field-effect passivation properties for p-type c-Si solar cells.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.