• Journal of the Korean Magnetics Society
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• v.20 no.5
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• pp.191-195
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• 2010

We have investigated the effect of the removal of an initial oxide layer and the anodization time on the growth of the porous alumina layer. The porous alumina layer was fabricated by two-step anodization process with phosphoric acid. We have observed the changes in the uniformity of the pore structure by varying the removing time of the initial oxide layer after the first anodization with phosphoric acid and chromic acid, and noted that its uniformity improves with the removing time. We have also determined the thickness of the alumina layer after the final anodization process and found that the thickness increases linearly with the anodization time. Under 150 V of anodization voltage with phosphoric acid, the growth rate of the porous alumina layer is determined to be 22.5 nm/min.

• ETRI Journal
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• v.27 no.1
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• pp.118-121
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• 2005

Silicon dioxide ($SiO_2$) films prepared by plasma-enhanced atomic-layer deposition were successfully grown at temperatures of $100\;to\;250^{\circ}C$, showing self-limiting characteristics. The growth rate decreases with an increasing deposition temperature. The relative dielectric constants of $SiO_2$ films are ranged from 4.5 to 7.7 with the decrease of growth temperature. A $SiO_2$ film grown at $250^{\circ}C$ exhibits a much lower leakage current than that grown at $100^{\circ}C$ due to its high film density and the fact that it contains deeper electron traps.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1040-1043
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• 2004

As time goes by, the market demand increases and each LCD panel manufacturing company makes every effort to produce more panels in a limited time. It is necessary to reduce the cost and time of production for the improvement of productivity in manufacturing companies. The increased speed of thin films growth used in the TFT process brings improvement of productivity but it is also accompanied by a drop in display quality due to a characteristic change of the thin film. So in our dissertation, we deal with the increased speed of a-Si layer growth and the proportioned a drop in characteristic quality. We discuss a drop in display quality by a characteristic change of a-Si layer and we propose a counter-plan through panel design improvement. We have already applied our plan to the 15" XGA panel and confirmed the improved result.

• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.233-238
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.957-960
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• 2008

The influences of silicon and MgO seed particle on the reconstruction characteristics of MgO protective layer were investigated to clarify the mechanism of reconstruction and exaggerated grain growth (EGG) in AC-PDP. The reconstruction and EGG are closely correlated with the driving force for nucleation and growth, interface energy and initial size distribution of MgO protective layer in plasma space during discharge in AC-PDP.

• Journal of Electrical Engineering and information Science
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• v.3 no.1
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• pp.110-116
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• 1998

A single-crystalline epitaxial film of GaAs has been grown on Si using a gs assisted-ionized vapour beam eptaxial technique. The native oxide layer on the silicon substrate was removed at 550$^{\circ}C$ by use of an accelerated arsenic ion beam, instead of a high-temperature desorption. During the growth the substrate temperature was maintained at 550$^{\circ}C$. Transmission electron microscopy and electron diffraction data suggest that the GaAs layer is an epitaxially grown single-crystalline layer. The possibility of growing device quality GaAs on Si is able demonstrated through fabrication of GaAs MODFET on Si substrates.

• Applied Science and Convergence Technology
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• v.26 no.5
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• pp.129-132
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• 2017

We report a chemical vapor deposition approach and optimized growth condition to the synthesis of single layer molybdenum disulfide ($MoS_2$). Obtaining large grain size with continuous $MoS_2$ atomically thin films is highly responsible to the growth distance between molybdenum trioxide source and receiving silicon substrate. Experimental results indicate that triangular shape $MoS_2$ grain size could be enlarged up to > 80um with the precisely controlled the source-to-substrate distance under 7.5 mm. Furthermore, we demonstrate fabrication of a memory device by employing poly(methyl methacrylate) (PMMA) as insulating layer. The fabricated devices have a PMMA-$MoS_2$/metal configuration and exhibit a bistable resistance switching behavior with high/low-current ratio around $10^3$.

• Journal of the Korean institute of surface engineering
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• v.27 no.2
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• pp.83-90
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• 1994

We have investigated the mechanism for the abnormal oxide growth occuring during oxidation of the crystalline tungsten silicide. TEM and XPS analysis reveal the abnormaly grown oxide layer consisting of crystalline $Wo_3$ and amorphous $SiO_2$. The presence of crystalline $Wo_3$ provides a rapid diffusion of oxygen through the oxide layer. The abnormal oxide growth is mainly due to the poor quality of initial oxide layer growth on tungsten silicide. Two species such as tungsten and silicon from decomposition fo tungsten silicide as well as silicon supplied from the underlying polysilicon are the main contributors sto abnormal oxide forma-tion. Consequently, the abnormal oxidation results in the disintegration of tungsten silicide and thinning of polysilicon as well.

• Journal of Ocean Engineering and Technology
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• v.16 no.2
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• pp.60-66
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• 2002

The remote measurement system(RMS) as a new experimental method is limited in its application to crack measurement at elevated temperatures because of the oxide layer on the specimen surface. Since TiAIN and Cr coating layers have a high resistance to oxidation and wear, this paper proposed a TiAIN and Cr coating technique for specimens to facilitate the measurement of crack growth behavior using RMS. To investigate the effects of the coating layer, tension and fatigue tests were carried out at room temperature and at $538^{\circ}C$. The test material was 1Cr-1Mo-0.25V steel which is widely used as a turbine rotor material. From the experimental results, it was found that the mechanical properties of the TiAIN and Cr coated specimens were similar to those of the substrate. Accordingly, the TiAIN and Cr coated layer had hardly any influence on the fatigue crack propagation.

• Electrical & Electronic Materials
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• v.7 no.4
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• pp.281-288
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• 1994

According to spread volume of B(BiPbCuO) layer, composition ratio and each stage of sintering process, we studied stability of high Tc superconductor phase and generation and growth movement of superconducting phase. The dual layer composed of SrCaCuO and BiPbCuO compound were prepared to develop the Bi-2223 superconductor[108K] through interaction and diffusion during sintering process. The dual layer samples were sintered at 830.deg. C for 0-210 hours. From the result, the optimum conditions were : spread volume(A:B=1:0.6), sintering time(210h) and composition ratio(A:S $r_{2}$C $a_{2}$C $u_{2}$- $O_{x}$, B:B $i_{1.9}$P $b_{0.5}$C $u_{3}$ $O_{y}$) at 830.deg. C.. C.C.C.