• 전자공학회논문지D
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• 제35D권9호
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• pp.54-61
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• 1998

Deep submicron급 CMOS디바이스에서 래치업 면역특성을 향상시키기 위한 새로운 Triple well구조를 제안하였다. Triple well에서 이온주입 에너지와 도즈량 변화에 따른 최적인 래치업 면역을 위한 공정조건을 확립하고 이것을 기존의 Twin well구조와 비교분석하였다. 공정은 공정시뮬레이터인 ATHENA로 소자를 제작하여 도핑프로파일과 구조를 해석하고 래치업 특성은 소자시뮬레이터인 ATLAS를 사용하였다. Triple well과 Twin well의 구조에서 공정상의 차이가 도핑프로파일에 미치는 영향과 프로파일 형태가 래치업 특성에 미치는 영향을 규명하였다. Triple well구조에서 p-well이온주입에너지 2.5MeV, 도즈량 1×10/sup 14/[cm/sup -2/]일 때 트리거 전류가 2.5[mA/${\mu}{m}$]로 매우 큰 래치업 면역특성을 얻었다.

• 한국산학기술학회논문지
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• 제6권1호
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• pp.54-57
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• 2005

반도체 소자 면적의 축소에 따라 중성자의 소프트 에러율은 집적회로 설계시 큰 문제점으로 대두되고 있다. 고전류 중성자 빔에 의한 가속 실험에서, 래치-업 현상은 소프트 에러 발생율의 정확한 예측을 방해하는 요소로 작용하고 있다. 본 연구는 SRAM 소자의 SER 가속 실험시 발생하는 래치-업에 대한 효과를 분석하였다. 2차원 소자 시뮬레이터를 이용한 시뮬레이션 환경하에서의 결과 깊은 p-well 구조의 기판이 이중 또는 삼중 well 구조에 비하여 양호한 래치-업 방지 효과를 나타내었다. 또한 접지에 대한 $V_{DD}$ 전력선까지의 거리를 최소화하는 것이 효과적인 설계 기법으로 평가되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1111-1113
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• 1995

To improve latch up characteristics of IGBT, this paper proposed new structure with reverse channel. IGBT proposed by this paper were designed on SOI substrate, $p^+$-substrate, and $n^+$-substrate, respectively. As a result of the simulation, we had achieved high latch up voltage and high conduction current density at IGBT with proposed structure. Latch up voltage of Conventional IGBT was 2.5V but IGBT with proposed structure was latched up at $5{\sim}94V$, respectively. And was showed high conduction current desity($10^4{\sim}10^7A/cm^2$)

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.865-868
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• 2001

We designed and fabricated a planner-type thermoelastic microactuator with a latch-up operation for optical switching. Latch-up actuation is prerequisite to implement an optical switch with low power consumption and high reliability. The proposed microactuator consists of four cantilever-shaped thermal actuators, four displacement linkages, two shallow arch-shaped leaf springs, a mobile shuttle mass with a micromirror, and four elastic boundaries. The structural layer of the planar microactuator is phosphorous-doped 12$\mu\textrm{m}$-thick polysilicon, and the sacrificial layer is LTO(Low Temperature Oxide) of 3$\mu\textrm{m}$thickness. The displacement of actuator is as large as 3$\mu\textrm{m}$when the length of actuation bar is 100$\mu\textrm{m}$in length at 5V input voltage. The proposed microactuators have advantages of easy assembly with other optical component by way of fiber alignment in the substrate plane, and its fabrication process features simplicity while retaining batch-fabrication economy.

• 한국전기전자재료학회논문지
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• 제17권10호
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• pp.1034-1040
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• 2004

The latch-up current and switching characteristics of MOS-Controlled Thyristor(MCT) are studied with variation of the channel length and impurity concentration. The proposed MCT power device has the lateral structure and P-epitaxial layer in substrate. Two dimensional MEDICI simulator is used to study the latch-up current and forward voltage-drop from the characteristics of I-V and the switching characteristics with variation of impurity concentration. The channel length and impurity concentration of the proposed MCT power device show the strong affect on the anode current and turn-off time. The increase of impurity concentration in P and N channels is found to give the increase of latch-up current and forward voltage-drop.

• 한국소음진동공학회논문집
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• 제14권4호
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• pp.287-294
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• 2004

Dynamic Load/unload (L/UL) mechanism is an alternative to the contact start stop (CSS) technology which eliminates striction and wear failure modes associated with CSS. Inertia latch mechanism becomes important for mobile disk drives because of non operating shock performance. Various types of latch designs have been introduced in hard disk drives to limit a rotary actuator from sudden uncontrolled motion. In this paper, a single spring inertia latch is introduced for a small form optical disk drive, which uses a rotary actuator for moving an optical pick-up. A new small inertia latch with sin91e spring is designed to ensure both feasible and small size. The shock performance of the new inertia latch is experimentally verified.

• 대한전기학회논문지
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• 제45권2호
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• pp.249-255
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• 1996

A self-aligned latch-up suppressed IGBT has been proposed and the process method and the device characteristics of the IGBT have been verified by numerical simulation. As the source is laterally diffused through the sidewall of the trench in the middle of the body, the size of the source is small and the doping concentration of the source is lower than that of the p++ body and the emitter efficiency of the parasitic npn transistor is low so that latch-up may be suppressed. No additional mask steps for p++ region, source, and source contact are required so that small sized body can be obtained Latch-u current density higher than 10000 A/cm$^{2}$ have been achieved by adjusting the process conditions.

• Transactions on Electrical and Electronic Materials
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• 제2권1호
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• pp.32-38
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• 2001

A new small sized Lateral Trench electrode Insulated Gate Bipolar Transistor(LTEIGBT) was proposed to improve the characteristics of conventional Lateral IGBT (LIGBT) and Lateral Trench gate IGBT (LTIGBT). The entire electrode of LTEIGBT was replace with trench-type electrode. The LTEIGBT was designed so that the width of device was no more than 19 ㎛. The Latch-up current densities of LIGBT, LTIGBT and the proposed LTEIGBT were 120A/㎠, 540A/㎠, and 1230A/㎠, respectively. The enhanced latch-up capability of the LTEIGBT was obtained through holes in the current directly reaching the cathode via the p+ cathode layer underneath n+ cathode layer. The forward blocking voltage of the LTEIGBT is 130V. Conventional LIGBT and LTIGBT of the same size were no more than 60V and 100V, respectively. Because the the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and punch through breakdown of LTEIGBT is occurred, lately.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.342-345
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• 2002

A new lateral trench electrode IGBT with p+ diverter was Proposed to suppress latch-up of LTIGBT. The p+ diverter was placed between the anode and cathode electrode. The latch-up of LTEIGBT with a p+ diverter was effectively suppressed to sustain an anode voltage of 8.7V and a current density of 1453A/$\textrm{cm}^2$ while in the conventional LTIGBT, latch-up occurred at an anode current density of 540A/$\textrm{cm}^2$. And the forward blocking voltage of the proposed LTEIGBT with a p+ diverter was about 140V. That of the conventional LTIGBT of the same size was no more than 105V. When the gate voltage is applied 12V, the forward conduction currents of the Proposed LTEIGBT with a p+ diverter and the conventional LIGBT are 90mA and 70mA, respectively, at the same breakdown voltage of 150V.

• 한국전기전자재료학회논문지
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• 제14권7호
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• pp.546-550
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• 2001

A new Lateral Trench Insulated Gate Bipolar Transistor(LTIGBT) with p$^{+}$ diverter was proposed to improve the characteristics of the conventional LTIGBT. The forward blocking voltage of the proposed LTIGBT with p$^{+}$ diverter was about 140V. That of the conventional LTIGBT of the same size was 105V. Because the p$^{+}$ diverter region of the proposed device was enclosed trench oxide layer, he electric field moved toward trench-oxide layer, and punch through breakdown of LTIGBT with p$^{+}$ diverter was occurred, lately. Therefore, the p$^{+}$ diverter of the proposed LTIGBT didn't relate to breakdown voltage in a different way the conventional LTIGBT. The Latch-up current densities of the conventional LTIGBT and proposed LTIGBT were 540A/$\textrm{cm}^2$, and 1453A/$\textrm{cm}^2$, respectively. The enhanced latch-up capability of the proposed LTIGBT was obtained through holes in the current directly reaching the cathode via the p$^{+}$ divert region and p$^{+}$ cathode layer beneath n$^{+}$ cathode layer./ cathode layer.