• 터널과지하공간
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• 제15권6호
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• pp.432-440
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• 2005

배후령 터널은 강원도 춘천과 화천을 연결하는 길이 5,057 m의 2차선 양방향 단선 터널로 장래 4차선으로 확장 될 계획이다. 본 터널은 55개월의 공기로 현재 시공 중이며 완공 후 국내 최장대 양방향 도로터널이 될 것이다. 양방향 단선터널은 복선터널에 비해 환기 및 화재 대처에 대한 단점을 가지고 있다. 이러한 이유로 배후령 터널에는 국내 최초로 연장 5,173 m, 직경 5 m의 서비스터널을 계획하였으며, 횡류식 환기방식을 적용하였다. 이 환기 시스템은 화재 시 제연효과로 대피자의 안전을 확보할 수 있다. 배후령 터널 구간은 편마암과 화강암을 기반암으로 하며, 터널 방향을 따라 큰 규모의 배후령 단층이 발달 되어있다. 이 단층의 영향 범위는 각종 조사 및 시험결과 약 70 m로 분석되어, 안전을 고려 터널 노선은 단층에서 100 m이상 이격하여 선정되었다.

• Progress in Superconductivity
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• 제10권1호
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• pp.45-49
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• 2008

For the development of superconducting fault current limiters (SFCLs), fault current limiting elements were fabricated out of Bi-2212 bulk tubes and tested. The SFCL elements consisted of tube shaped Bi-2212 bulks and metal shunts for the stabilizers. Firstly, the Bi-2212 bulk tubes were processed based on a design of monofilar coils in order to acquire large resistance and high voltage rating. 300 mm-long Bi-2212 tubes were designed to have the current path of 410 cm in length with 24 turns and 41 mm in diameter. The processed monofilar coil, as designed, had 300 A $I_c$ at 77 K. The fabricated superconducting monofilar coils were affixed to Cu-Ni alloy as that of stabilizers. The Cu-Ni alloys were processed to have the same shape of the superconducting monofilar coils. The Cu-Ni coil had resistivity of 32 ${\mu}{\Omega}$-cm at 77 K and 37 ${\mu}{\Omega}$-cm at 300 K. The metal shunts were attached to the outside of the Bi-2212 monofilar coil by a soldering technique. After the terminals made of copper were attached to both ends of the superconductor-metal shunt composite, the gap between the turns and the surface of the elements was filled with an epoxy and a dense mesh made of FRP in order to enhance the mechanical strength. The completed SFCL elements went through fault tests, and we confirmed that the voltage rating of 143 $V_{rms}$ (E =0.35 $V_{rms}$/cm) could be accomplished.

• 대한전자공학회논문지SD
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• 제38권1호
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• pp.44-54
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• 2001

본 논문에서는 아날로그 회로에 존재하는 강고장(hard fault)과 약고장(soft fault)을 검출하기 위한 새로운 테스트 방식을 제안한다. 제안한 테스트 방식은 연산 증폭기의 특성중 하나인 오프셋 전압(offset voltage)을 이용한다. 테스트 시, 테스트 대상 회로(CUT: Circuit Under Test)는 귀환 루프를 가지는 단일 이득 연산 증폭기로 변환된다. 연산 증폭기의 입력이 접지되었을 때, 정상 회로는 작은 오프셋 전압을 가지지만 고장이 존재하는 회로는 큰 오프셋 전압을 가진다. 따라서 오프셋 전압의 허용 오차를 벗어나는 연산증폭기 내에 존재하는 고장들을 검출할 수 있다. 제안한 테스트 방식은 테스트 패턴 없이 단지 입력을 접지시키면 되므로 테스트 패턴을 생성하는 문제를 제거시킬 수 있어 테스트 시간과 비용이 감소한다. HSPICE 모의 실험을 통하여 본 논문에서 제안하는 방식을 단일 연산증폭기와 듀얼 슬롭(dual slope) A／D 변환기에 적용한 결과 높은 고장 검출율(fault coverage)을 얻었다.

• 한국초전도ㆍ저온공학회논문지
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• 제8권2호
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• pp.29-32
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• 2006

An advanced superconducting fault current limiter (SFCL) using $high-T_c$ superconducting (HTS) wire has been developed. The SFCL has a non-inductively wound magnet for reducing loss in normal state. Two types of non-inductively wound magnets, the solenoid type and the pancake type, were designed and manufactured by using Bi-2223 wire in this research. Short-circuit tests of the magnets were performed in sub-cooled $LN_2$ cooling system of 65 K. The magnets are thermally more stable and have a higher critical current in 65 K sub-cooled $LN_2$ cooling system than in 77 K saturated one. Because the resistivity of matrix at 65 K is lower than the resistivity at 77 K, the magnets generate a small resistance to reduce the fault current when the quench occurs. The magnets could limit the fault current to low current level with such a small resistance. The current limiting characteristic of the magnets was analyzed from the test result. The solenoid type was wound in parallel to make it non-inductive. The pancake type was also connected in parallel to be compared with the solenoid type in the same condition. The solenoid type was found to have a good thermal stability compared with the pancake type. It also had as large resistance as the pancake type to limit the fault current in sub-cooled $LN_2$ cooling system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.811-814
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• 1998

REcent research about current testing($\textrm{I}_{DDQ}$ testing) has been emphasizing that $\textrm{I}_{DDQ}$ testing in addition to the logical voltage testing is necessary to increase the fault coverage. The $\textrm{I}_{DDQ}$. testing can detect physical faults other than the classical stuck-at type fault, which affect reliability. One of the most critical issues in the $\textrm{I}_{DDQ}$ testing is to insert a built-in current sensor (BICS) that can detect abnormal static currents from the power supply or to the ground. This paper presents a new BICS for internal current testing for large CMOS logic circuits. The proposed BICS uses a single phase clock to minimize the hardware overhead. It detects faulty current flowing and converts it into a corresponding logic voltage level to make converts it into a corresponding logic voltage level to make it possible to use the conventional voltage testing techniqeus. By using current mirroring technique, the proposed BICS can work at very high speed. Because the proposed BICS almost does not affects normal operation of CUT(circuit under test), it can be used to a very large circuit without circuit partitioning. By altenating the operational modes, a circuit can be $\textrm{I}_{DDQ}$-tested as a kind of self-testing fashion by using the proposed BICS.

• Nuclear Engineering and Technology
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• 제44권7호
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• pp.755-766
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• 2012

A Binary Decision Diagram (BDD) is a graph-based data structure that calculates an exact top event probability (TEP). It has been a very difficult task to develop an efficient BDD algorithm that can solve a large problem since its memory consumption is very high. Recently, in order to solve a large reliability problem within limited computational resources, Jung presented an efficient method to maintain a small BDD size by a BDD truncation during a BDD calculation. In this paper, it is first identified that Jung's BDD truncation algorithm can be improved for a more practical use. Then, a more efficient truncation algorithm is proposed in this paper, which can generate truncated BDD with smaller size and approximate TEP with smaller truncation error. Empirical results showed this new algorithm uses slightly less running time and slightly more storage usage than Jung's algorithm. It was also found, that designing a truncation algorithm with ideal features for every possible fault tree is very difficult, if not impossible. The so-called ideal features of this paper would be that with the decrease of truncation limits, the size of truncated BDD converges to the size of exact BDD, but should never be larger than exact BDD.

• 한국초전도ㆍ저온공학회논문지
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• 제17권1호
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• pp.1-5
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• 2015

With the increasing development of renewable energy, it is expected that large-scale renewable power would be transported from the west and north area of China to the east and south area. For this reason, it will be necessary to develop a wide-area power grid in which the renewable energy would be the dominant power source, and the power grid will be faced by some critical challenges such as long-distance large-capacity power transmission, the stability of the wide-area power grid and the land use problem for the power grid. The superconducting technology for power (STP) would be a possible alternative for the development of China's future power grid. In last decade, STP has been extensively developed in China. In this paper, we present an overview of the R&D of STP last decade in China including: 1) the development of high temperature superconducting (HTS) materials, 2) DC power cables, 3) superconducting power substations, 4) fault current limiters and 5) superconducting magnetic energy storage (SMES).

• Smart Structures and Systems
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• 제29권3호
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• pp.485-498
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• 2022

In near-fault earthquake prone areas, the velocity pulse-like seismic waves often results in excessive horizontal displacement for structures, which may result in severe structural failure during large or near-fault earthquakes. The recently developed isolator-gap damper (IGD) systems provide a solution for the large horizontal displacement of long period base-isolated structures. However, the hysteresis characteristics of the IGD system are significantly different from the traditional hysteretic behavior. At present, the hysteretic behavior is difficult to be reflected in the structural analysis and performance evaluation especially under random earthquake excitations for lacking of effective analysis models which prevent the application of this kind of IGD system. In this paper, we propose a mathematical hysteretic model for the IGD system that presents its nonlinear hysteretic characteristics. The equivalent linearization is conducted on this nonlinear model, which requires the variances of the IGD responses. The covariance matrix for the responses of the structure and the IGD system is obtained for random earthquake excitations represented by the Kanai-Tajimi spectrum by solving the Lyapunov equation. The responses obtained by the equivalent linearization are verified in comparison with the nonlinear responses by the Monte Carlo simulation (MCS) analysis for random earthquake excitations.

• 한국지반환경공학회 논문집
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• 제16권5호
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• pp.43-53
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• 2015

본 연구에서는 빅데이터 범주에 포함되는 각종 계측 데이터를 대상으로 각종 이상치를 판단하기 위한 기법을 고안하고, 인공 데이터 및 실 계측 데이터를 이용한 이상치 분석을 수행하였다. 계측결과에 대한 1차 차분 값 및 오차율을 적용한 규칙기반 방법은 큰 규모의 Short fault 분석 및 일정 기간 계측값에 변화가 발생하지 않는 경우의 Constant fault 분석에 효과적으로 적용될 수 있었으나, 독립적인 단일 데이터셋만을 이용하는 관계로 큰 변화폭을 보이는 실 계측 데이터의 정상 데이터를 이상치로 오판하는 문제점이 있었다. 규칙기반 방법을 이용한 Noise fault 분석은 적정 데이터 윈도우 사이즈의 선택 및 이상치 판정용 한계값 선정상의 문제로 인해 실 계측 데이터 적용에 한계가 있었다. 이종 데이터 간 상관분석 방법은 학습 데이터의 적정범위 선정이 선행된다면 장단기 계측 데이터의 이상 거동 및 국부적 이상치 판정에 매우 효과적으로 이용될 수 있음을 알 수 있었다.

• 전기의세계
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• 제23권1호
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• pp.61-68
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• 1974

This paper attempts to develop the algorithms and computer program for load flow solution and faults analysis of large power system by small digital computer. The Conventional methods for load flow solution and fault analysis of large power system require too much amount of computer memory space and computing time. Therefore, this paper describes the methad for reducing the computer memory space and computing time as follows. (1) Load Flow Solution; This method is to store each primitive impedance of lines along with a list of bus numbers corresponding to the both terminals of lines, and to store only nonzero element of bus admittance matrix. (2) Faults Analysis: This method is to partition a large power system into several groups of subsystems, form individual bus impedance matrix, store them in the storage, and assemble the only required portion of them to original total system by algorithm.