• Journal of Information Display
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• v.10 no.3
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• pp.117-120
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• 2009

A new crystallization method for amorphous silicon, called selective area heating (SAH), was proposed. The purpose of SAH is to improve the reliability of amorphous silicon films with extremely low thermal budgets to the glass substrate. The crystallization time shortened from that of the conventional solid-phase crystallization method. An isolated thin heater for SAH was fabricated on a quartz substrate with a Pt layer. To investigate the crystalline properties, Raman scattering spectra were used. The crystalline transverse optic phonon peak was at about 519 $cm^{-1}$, which shows that the films were crystallized. The effect of the crystallization time on the varying thickness of the $SiO_2$ films was investigated. The crystallization area in the 400nm-thick $SiO_2$ film was larger than those of the $SiO_2$ films with other thicknesses after SAH at 16 W for 2 min. The results show that a $SiO_2$ capping layer acts as storage layer for thermal energy. SAH is thus suggested as a new crystallization method for large-area electronic device applications.

• Korean Journal of Materials Research
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• v.19 no.8
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• pp.437-442
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• 2009

This paper describes an improved strategy for controlling the adhesion force using both the antiadhesion and adhesion layers for a successful large-area transfer process. An MPTMS (3-mercaptopropyltrimethoxysilane) monolayer as an adhesion layer for Au/Pd thin films was deposited on Si substrates by vapor self assembly monolayer (VSAM) method. Contact angle, surface energy, film thickness, friction force, and roughness were considered for finding the optimized conditions. The sputtered Au/Pd ($\sim$17 nm) layer on the PDMS stamp without the anti-adhesion layer showed poor transfer results due to the high adhesion between sputtered Au/Pd and PDMS. In order to reduce the adhesion between Au/Pd and PDMS, an anti-adhesion monolayer was coated on the PDMS stamp using FOTS (perfluorooctyltrichlorosilane) after $O_2$ plasma treatment. The transfer process with the anti-adhesion layer gave good transfer results over a large area (20 mm $\times$ 20 mm) without pattern loss or distortion. To investigate the applied pressure effect, the PDMS stamp was sandwiched after 90$^{\circ}$ rotation on the MPTMS-coated patterned Si substrate with 1-${\mu}m$ depth. The sputtered Au/Pd was transferred onto the contact area, making square metal patterns on the top of the patterned Si structures. Applying low pressure helped to remove voids and to make conformal contact; however, high pressure yielded irregular transfer results due to PDMS stamp deformation. One of key parameters to success of this transfer process is the controllability of the adhesion force between the stamp and the target substrate. This technique offers high reliability during the transfer process, which suggests a potential building method for future functional structures.

• Applied Chemistry for Engineering
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• v.35 no.1
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• pp.61-65
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• 2024

The effectiveness of CuSCN as a hole injection layer in large-area organic light-emitting diodes, organic solar cells, and thin-film transistors has been well demonstrated. Therefore, in this study, the surface, optical, and electrical analyses of CuSCN were carried out according to the solution process conditions in order to propose optimized film conditions. Various CuSCN solution concentrations were prepared to determine the film surface characteristics and to determine whether the film surface affects the electrical performance of the device. When the CuSCN solution concentration was low, the CuSCN film was not formed and coated in the form of islands, and when the solution concentration was increased, the CuSCN film was formed uniformly, which contributed to improving the conductivity of the device. In addition, a hole-only device was fabricated to demonstrate the role of CuSCN as a hole transport layer.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.4 no.2
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• pp.119-130
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• 1994

To deposit silicon on borosilicate glass substrates, 18 different substrate combinations were investigated because of the difficulty of direct deposition of silicon. Sucessful results were obtained from Al-and Mg-treated glass and furnace annealed sputtered silicon deposited glass substrates. A continuous silicon thin film on a large area substrates was obtained in the temperatures ranges from $420^{\circ}C to 520^{\circ}C$. These thin films might be applied to lower the cost of solar cells and solar cell modules.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.923-926
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• 2004

Active-matrix field emission display (AMFED) based on carbon nanotube (CNT) emitter and amorphous silicon thin-film transistor (a-Si TFT) is reviewed. The AMFED pixels consisted of a high-voltage a-Si TFT and mesh-gated CNT emitters. The developed AMFED panel showed a high performance with a driving voltage of below 15 V. The low-cost and large-area AMFED approach with a metal mesh technology will be discussed.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.398-401
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• 2008

Inkjet printing is commonly used in the controlled deposition of solutions of functional materials in specific locations on a substrate, and it can provide easy and fast deposition of polymer films over a large area. which could become a way to manufacturer low cost solar cells. In the present study, inkjet printing technology is adopted to deposit functional layers of PEDOT/PSS solutions and P3HT/PCBM blends for organic solar cell. The results show that merging of separately deposited ink droplets into a continuous, pinhole-free organic thin film could be achieved by a balance between ink property and substrate treatment. As a result, a power conversion efficiency of 2.0% has been accomplished a solar cells applying inkjet technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.137-140
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• 1998

An active-matrix LCD using thin film transistors (TFT) has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate si후미 distortion and pixel charging capability. which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate, data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the resistivity of gate line material on the pixel operations can be effectively analyzed. The gate signal delay, pixel charging ratio and level-shift of the pixel voltage were simulated with varying the parameters. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.699-702
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• 2004

Next generation lithography technologies, such as EBL(Electron Beam Lithography), X-ray lithography, SPL(Scanning Probe Lithography), have been studied widely for getting over line width limitation of photolithography. Among the next generation lithography technologies, SPL has been highlighted because of its high resolution advantage. But is also has problem which are slow processing time and sample size limitation. The purpose of this study is complement of present SPL system. Brand new SPL system was made. SPL test was performed with the system in ultra thin PMMA(polymethlymethacrylate) film.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.233-236
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• 2000

Polycrystalline Silicon Thin Film Transistors(Poly-Si TFT's), fabricated at temperature lower than $600^{\circ}C$ are now largely used in many applications, particularly in large area electrons. In this work, electrical stress effects on Poly-Si TFT's fabricated by Solid Phase Crystal(SPC) was investigated by measuring electric properities such as transfer and output characteristics, and channel conductance. Consequently, It is turned out that it should be noted the output characteristics, drain current and channel conductance, strongly degrade around origin.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1462-1464
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• 1998

Poly-Si TFT(Thin Film Transistor) is a electronic device that can be applied to the field of large area electronics such as AMLCD. We have fabricated the poly-Si TFT with lateral body terminal that is counter-doped body electrode and investigated the electrical characteristics of it. The lateral body terminal being short with s terminal, we have measured the transfer charac (Vg-ld) and the output characteristic (Vd-ld) fabricated devices. The measured result showe only that leakage current in OFF-state was re and Kink effect in ON-state was suppressed bu that in output characteristic curve the output Id was sustained constantly with the output v Vd in the saturation region.