• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.187-189
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• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.64.1-64.1
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• 2012

Next generation displays such as high performance LCD, AMOLED, flexible display and transparent display require specific TFT back-planes. For high performance TFT back-planes, low temperature poly silicon (LTPS), and metal-oxide semiconductors are studied. Flexible TFT backplanes require low temperature processible organic semiconductors. Not only development of active semiconducting materials but also design and synthesis of semiconductor corresponding gate dielectric materials are important issues in those display back-planes. In this study, we investigate the high heat resistant polymeric gate dielectric materials for organic TFT and inorganic TFT with good insulating properties and processing chemical resistance. We also controlled and optimized surface energy and morphology of gate dielectric layers for direct printing process with solution processible organic and inorganic semiconductors.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.841-842
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• 2006

This paper has proposed a serial 8-bit DAC for column driver circuits of mobile displays using LTPS TFTs. The DAC circuit takes very small area by using parasitic capacitance of column lines as sampling and holding capacitors. Moreover, the proposed DAC does not need the analog buffer, because the DAC operation is performed on the column lines. For the data driver circuits of 2-inch qVGA OLED panel, the DAC area is $84um{\times}800um$ and the simulated DAC power consumption is 8.5mW with 10-V supply voltage.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.258-261
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• 2009

In this work we present a process to fabricate lowtemperature polysilicon (LTPS) TFTs on polyimide (PI) layers, spin-coated on Si-wafer used as rigid carrier. This process has been then used to fabricate elementary circuits as well as circuits for sensor applications.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.945-947
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• 2009

We developed a new laser irradiation (BLDA: Blue Multi-Laser-Diode Annealing) system. The system forms the uniform line beam, which is constructed by 48 pieces of semiconductor lasers. This new system has achieved high laser output stability and the highly accurate beam shape by adopting a reliable laser control, the auto-focus control in addition to an original laser photosynthesis technology and the beam homogenizing technology. It was confirmed to crystallize the Si films effectively with good quality.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.378-381
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• 2009

As a Joule-heat source, a conductive Mo layer was used to crystallize amorphous silicon for AMOLED backplanes. This Joule-heating induced crystallization (JIC) process could produce poly-Si having a grain size ranging from tens of nanometers to greater than several micrometers. Here, the blanket (single-shot whole-plane) crystallization could be achieved on the $2^{nd}$ and the $4^{th}$ generation glass substrate.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.8-11
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• 2007

The new technologies in mobile display developed in SEC are briefly reviewed. For a differentiation, SEC's LTPS line is based on SLS (Sequential Lateral Solidification) technology. In this paper, the characteristics of SEC's SLS in recent and future mobile displays were discussed. The microstructure produced by SLS crystallization is dependent on SLS process conditions such as mask design, laser energy density, and pulse duration time. The microstructure and TFT (Thin Film Transistor) performance are closely related. For an optimization of TFT performance, SLS process condition should be adjusted. Other fabrication processes except crystallization such as blocking layer, gate insulator deposition and cleaning also affect TFT performance. Optimized process condition and tailoring mask design can make it possible to produce high quality AMOLED devices. The TFT non-uniformity caused by laser energy density fluctuation could be successfully diminished by mixing technology.

• Journal of Information Display
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• v.6 no.4
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• Journal of Information Display
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• v.7 no.3
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• pp.9-12
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• 2006

A new voltage-scaled compensation pixel which employs 3 p-type poly-Si TFTs and 2 capacitors without additional control line has been proposed and verified. The proposed pixel does not employ the $V_{TH}$ memorizing and cancellation, but scales down the inevitable $V_{TH}$ variation of poly-Si TFT. Also the troublesome narrow input range of $V_{DATA}$ is increased and the $V_{DD}$ supply voltage drop is suppressed. In our experimental results, the OLED current error is successfully compensated by easily controlling the proposed voltage scaling effects.

• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.