• Journal of Communications and Networks
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• v.16 no.4
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• pp.385-396
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• 2014

In this paper, we present a formal method for modeling and checking an enhanced version of the carrier sense multiple access with collision avoidance protocol related to the IEEE 802.11 MAC layer, which has been proposed as the standard protocol for wireless local area networks. We deal mainly with the distributed coordination function (DCF) procedure of this protocol throughout a sequence of transformation steps. First, we use the unified modeling language state machines to thoroughly capture the behavior of wireless stations implementing a DCF, and then translate them into the input language of the UPPAAL model checking tool, which is a network of communicating timed automata. Finally, we proceed by checking of some of the safety and liveness properties, such as deadlock-freedom, using this tool.

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.289-296
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• 1999

The integration of the LSI has been greatly improved and the circuit patters on the LSI are becoming finer line and pitch. The high-density electronic packaging technology is improved. In order to realize the high-density packaging technology, the density of the circuit wiring of the printed circuit boards have also been more dense. The build-up process multilayer printed circuit board technology have a lot of vias, possibilities of the finer conductor wirings and have a freedom of capabilities of wiring design. The build-up process printed circuit boards have the wiring rules which are the pattern width: $100-20\mu\textrm{m}$, the via hole diameter: $100-50\mu\textrm{m}$. There three kinds of build-up processes as far materials and hole drilling. In this paper, the recent technology trends of the build-up printed circuit board technologies are described.

• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.19-29
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• 2019

Requirements traceability is regarded as one of the important quality attributes in software requirements engineering field. If requirements traceability is guaranteed then we can trace the requirements' life throughout all the phases, from the customers' needs in the early stage of the project to requirements specification, deployment, and maintenance phase. This includes not only tracking the development artifacts that accompany the requirements, but also tracking backwards from the development artifacts to the initial customer requirements associated with them. In this paper, especially, we dealt with the traceability between functional requirements and non-functional requirements. Among many Information Retrieval (IR) techniques, we decided to utilize Latent Semantic Indexing (LSI) and Latent Dirichlet Allocation (LDA) in our research. Ultimately, we conducted an experiment on constructing traceability by using two techniques and analyzed the experiment results. And then we provided a comparative study between two IR techniques in constructing traceability between functional requirements and non-functional requirements.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.11a
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• pp.1010-1011
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• 2023

코로나19 팬데믹 이후 배달 앱 사용량이 증가에 따라 배달 오토바이 수가 급증하면서 이와 관련 사고 또한 급격히 증가하는 추세를 보이고 있다. 특히 청각 장애인들은 도로에서 이러한 종류의 사고 위험에 더욱 노출되어 있으며, 이 문제를 해결하기 위해 구글 앱 인벤터를 사용하여 도로에서 오토바이 소리를 인식하는 인공지능 학습 모델을 개발하였다. 개발된 어플리케이션은 도로에서 오토바이 소리를 감지하고 사용자에게 진동과 사진으로 알림을 보냄으로써 사고를 예방에 기여할 수 있다.

• The Science & Technology
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• v.16 no.7 s.170
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• pp.21-24
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• 1983

- 미 퍼스널 컴퓨터 이용패턴 - 미국의 목성, 금성 탐사계획 - 미반도체 메이커들 협동연구 - 말하는 팔뚝시계 등장 - 미, 중공에 LSI 생산시설 판매하기로

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• The Journal of Korean Institute for Practical Engineering Education
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• v.4 no.1
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• pp.30-44
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• 2012

The purposes of this study were to develop Korean version of the Kolb learning Style Inventory (version 3.1) by systematic translation process and to test learning style of 596 K University-students. First, Korean version of LSI was successfully developed and tested for ensuring internal consistency reliability and internal validity. Second, K University students' average scores of learning modes were as follows: 27.75 of Concrete Experience(CE), 27.93 of Reflective Observation(RO), Abstract 31,95 of Conceptualization (AC), and 32.37 of Active Experimentation(AE). In addition, the study reported KUT students learning style distribution: 32% of accommodating style, 27.2% of Diverging one, 26.5% of Assimilating one, and 14.3% of Converging one.

• Transactions of the Society of Information Storage Systems
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• v.2 no.4
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• pp.224-229
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• 2006

There has been studied flow to minimize the spot size to increase data capacity. Optical data storage devices are being developed near practical limits with wavelength and NA of 405nm and 0.85. There has been studied many types of next generation storage devices such as blu-ray multilayer system, probe based data storage and holographic data storage. Among these data storage devices, solid immersion lens(SIL) based near field recording (NFR) has been widely studied. In this system, SIL is the key component that focuses the laser beam with a very small size which enables ultra high data capacity. Therefore, optical performance evaluation system is required for SIL assembly. In this dissertation, a simple and accurate SIL assembly measurement method is proposed with wedge plate lateral shearing interferometer(LSI). Wedge plate LSI is cheaper than commercialized interferometer, robust to the vibration and the moving distance for phase shifting is large that is order of micrometer. We designed the thickness, wedge angle, material, surface quality and wavelength of wedge plate as 1mm, 0.02degree, fused silica, lamda/10(10-5) and 405nm, respectively. Also, we confirmed simulation and experimental results with quantitative analysis. This simple wedge plate LSI can be applied to different types of SIL such as solid immersion mirror(SIM), hemispherical, super-hemispherical and elliptical SIL.

• Journal of Korean Society for Geospatial Information Science
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• v.25 no.1
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• pp.19-27
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• 2017

This research was aimed to analyze landslide susceptibility and compare the prediction accuracy using ensemble frequency ratio (FR) and logistic regression at the Inje area, Korea. The landslide locations were identified with the before and after aerial photographs of landslide occurrence that were randomly selected for training (70%) and validation (30%). The total twelve landslide-related factors were elevation, slope, aspect, distance to drainage, topographic wetness index, stream power index, soil texture, soil sickness, timber age, timber diameter, timber density, and timber type. The spatial relationship between landslide occurrence and landslide-related factors was analyzed using FR and ensemble model. The produced LSI maps were validated and compared using relative operating characteristics (ROC) curve. The prediction accuracy of produced ensemble LSI map was about 2% higher than FR LSI map. The LSI map produced in this research could be used to establish land use planning and mitigate the damages caused by disaster.