• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1019-1024
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• 2005

MPEG-2 achieves high compression radio, by exploiting the temporal and spatial correlations in real image sequence, using the motion compensated prediction and the transform coding, respectively. However, as the image sequence is more highly compressed, the encoded bitstream becomes more vulnerable to transmission error over the noisy channels. Furthermore, er개rs in the headers are fatal to decoding processes, because the header parameters in the video coding standard include a lot of important information connected to the syntax elements, fables, and decoding process. In this paper, we propose a new error resilience method using LSB coding for header parameters in MPEG-2 coded video transmissions. The experimental results for football and susie video sequence demonstrate that the proposed error resilience method for header parameters in MPEG-2 bitstream has good performance.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.719-722
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• 2001

최근 정지영상, 동영상, 음성 등의 멀티미디어 컨텐트가 디지털화 되고 네트워크가 발달함에 따라 영상을 포함한 멀티미디어 데이터의 접근이 용이해 졌다. 이러한 데이터의 불법적 사용과 인위적인 조작으로부터 소유권과 저작권을 효율적으로 보호하기 위한 워터마킹 기술이 많이 연구되고 있다. 일반적으로 정지 영상 및 음성에 대한 워터마킹 기술은 많이 연구가 되었지만 이러한 방법을 동영상에 그대로 적용하기에는 실시간 처리에 적용하기가 힘들다는 큰 문제점이 있다. 따라서 본 논문에서는 비디오 신호에서의 빠른 처리과정과 실시간으로 워터마크를 삽입하고, 원 영상 없이 워터마크를 추출 할 수 있는 새로운 방법(Blind Watermarking)을 제안하고자 한다. 제안한 방법은 대역확산을 근거로 하여 워터마크 은닉 과정에서 치환(Permutation) 과정과 LSB 부호화 방법을 이용하여 비디오 시퀀스의 모든 I-프레임에 은닉한다. 복원과정은 모든 I-프레임에서 LSB 복호화와 역 치환 과정을 거쳐 본래의 저작권 정보를 추출한다. 제안한 방법을 여러 가지 동영상 비디오에 적용해 본 결과 기존의 워터마킹 방법보다 효율적이고 시각적 손상이 없었으며 빠른 실시간 처리가 가능함을 볼 수 있었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.3
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• pp.192-199
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• 2018

This paper proposes an improved discrete Fourier transform spread single sideband(DFT-s-SSB) orthogonal frequency division multiplexing(OFDM) system that solves the problems of conventional DFT-s-SSB OFDM systems. Conventional DFT-s-SSB systems use pulse amplitude modulation(PAM) for applying SSB modulation. The higher the modulation level, the worse is the BER performance. Further, transmission is possible only through the lower sideband(LSB) spectrum. When transmitting using the LSB and upper sideband(USB) spectra simultaneously, interference occurs and spectrum recovery is not performed correctly. To solve this problem, the proposed system applies the 2/3 convolution coding to improve the bit error rate(BER) performance, adjusts the DFT size, and selects the USB spectrum to utilize the remaining spectrum resources. In addition, when using this system in an environment that supports multiuser or limited bandwidth, it uses only half of the spectrum; therefore, it can utilize the remaining spectrum resources and improve the spectral efficiency.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.4
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• pp.243-249
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• 2016

This paper proposes a new watermarking algorithm to embed watermarks in thr process of sample adaptive offsets (SAO) for high efficiency video coding (HEVC) compressed videos. The proposed method embeds two-bit watermark into the SAO offsets for each coding tree unit (CTU). To minimize visual quality degradation caused by embedding watermark, watermark bits are embedded into SAO offset depending on the SAO types of block. Furthermore, the embedded watermark can be extracted by simply adding four offsets and checking their least significant bits (LSB) at the decoder side. The experimental results show that the proposed method achieves 0.3% BD-rate increase without much visual quality degradation. Two-bit watermark for each CTU is embedded for more bit watermarking. In addition, the proposed method requires negligible computational load for watermark insertion and extraction.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.152-161
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• 1996

In tis work, a three-stage pipelined A/D converter (ADC) was implemented to obtain 10-bit resolution at a conversion rate of 20 msamples/s for video applications. The ADC consists of three identical stages employing a mid-rise coding technique. The interstage errors such as offsets and clock feedthrough are digitally corrected in digitral logic by one overlapped bit between stages. The proposed ADC is optimized by adopting a unit-capacitor array architecture in the MDAC to improve the differential nonlinearity and the yield. Reduced power dissipation has been achieve dby using low-power latched comparators. The prototype was fabricated in a 0.8$\mu$m p-well CMOS technology. The ADC dissipates 160 mW at a 20 MHz clock rate with a 5 V single supply voltage and occupies a die area of 7 mm$^{2}$(2.7 mm $\times$ 2.6mm) including bonding pads and stand-alone internal bias circuit. The typical differential and integral nonlinarities of the prototype are less than $\pm$ 0.6 LSB and $\pm$ 1 LSB, respectively.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5B
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• pp.572-581
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• 2001

본 논문에서는 위성통신에서 강우감쇠에 따라 가변 부호화율을 적용시킬 수 있는 적응형 부호화 기법에 대한 연구를 하였다. 따라서, 3bit 연판정을 적용한 Viterbi 복호기를 이용하여 QPSK와 TC-8PSK 신호를 복호할 수 있는 pragmatic TCM과 LSB 부호화 알고리즘에 대해 여러 부호화율에서 성능분석을 하였다. 또한 구현을 위한 최적의 파라미터를 설정하여 부호화율 2/3를 가지는 pragmatic TCM을 VHDL 모델링 하였다. 구현결과 PLEX10KE100EQC208-1 CPLD 칩으로 구현 가능하였으며, 42.36 Mbps의 복호 속도를 가진다. 실제 ASIC 설계시 CPLD 속도보다 약 5∼6배의 고속화가 가능하므로, 200 MHz 트렌스 폰더를 갖는 Ka 대역 초고속 위성통신 시스템에서 강우 감쇠에 대처하기 위한 적응형 트렐리스 부호화방식에 적용할 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2C
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• pp.181-188
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• 2007

This paper proposed a watermark embedding/extracting method using CABAC(Context-based Adaptive Binary Arithmetic Coding) which is the entropy encoder for the main profile of MPEG-4 Part 10 H.264/AVC. This algorithm selects the blocks and the coefficients in a block on the bases of the contexts extracted from the relationship to the adjacent blocks and coefficients. A watermark bit is embedded without any modification of coefficient or with replacing the LSB(Least Significant Bit) of the coefficient with a watermark bit by considering both the absolute value of the selected coefficient and the watermark bit. Therefore, it makes it hard for an attacker to find out the watermarked locations. By selecting a few coefficients near the DC coefficient according to the contexts, this algorithm satisfies the robustness requirement. From the results from experiments with various kinds and various strengths of attacks the maximum error ratio of the extracted watermark was 5.02% in maximum, which makes certain that the proposed algorithm has very high level of robustness. Because it embeds the watermark during the context modeling and binarization process of CABAC, the additional amount of calculation for locating and selecting the coefficients to embed watermark is very small. Consequently, it is highly expected that it is very useful in the application area that the video must be compressed right after acquisition.