• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.25-32
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• 2014

In this paper, we proposed a partial-way set associative cache memory with an effective memory access time and low energy consumption. In the proposed set-associative cache memory, it is allowed to access only a 2-ways among 4-way at a time. Choosing ways to be accessed is made dynamically via the least significant two bits of the tag. The chosen 2 ways are sequentially accessed by the way selection bits that indicate the most recently referred way. Therefore, each entry in the way has an additional bit, that is, the way selection bit. In addition, instead of the 4-way LRU or FIFO algorithm, we can utilize a simple 2-way replacement policy. Simulation results show that the energy*delay product can be reduced by about 78%, 14%, 39%, and 15% compared with a 4-way set associative cache, a sequential-way cache, a way-tracking cache, and a way cache respectively.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.11 no.3
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• pp.43-52
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• 2007

A hard disk, which can be classified as an external storage is usually capacious and economical. In spite of the attractive characteristics and efforts on the performance improvement, however, the operation of the hard disk is apparently slower than a processor and the advancement has also been slowly conducted since it is based on mechanical process. On the other hand, the advancement of the processor has been drastically performed as semiconductor technology does. So, disk I/O sub-system becomes bottleneck of computer systems' performance. For this reason, the research on disk I/O sub-system is in progress to improve computer systems' performance. In this paper, we proposed multi-level LRU scheme and then apply it to the computer systems with buffer cache and disk cache. By applying the proposed scheme to computer systems, the average access time to disk blocks can be decreased. The efficiency of the proposed algorithm was verified by simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1229-1240
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• 1998

In this paper, we provide a design of DAVIC VOD service system with proxy servers which perform caching of video streams. Proxy servers are placed between a service provider system and service consumer systems. They provide video services to consumers on behalf of the service provider, therefore they reduce the loads of service providers and network. The operation of a proxy server depends on whether the requested program is in its storage. If this is the case, the prosy servere takes all the controls, but if the proxy does not have the program, it forwards the service request the proxy server takes all the controls, but if the prosy does not have the program, it forwards the service request to a service provider. While the service provider system provides the program to the consumer, the proxy copies and caches the program. The proxy server executes cache replacement, if necessary. We show by simultion that the LFU is the most efficiency caching replacement algorithm among the typical algorithms such as LRU, LFU, FIFO.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.64-71
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• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.

• Journal of Internet Computing and Services
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• v.5 no.1
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• pp.15-23
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• 2004

This paper presents distributive web-caching technique on the Head-End-Network (HNET) to solve excessive load of multimedia sever and inefficient use of network resources, The proposed web-caching is not concentration of load for a specific Head-End-Node(HEN), and it has advantage that there is no copy of a specific item on distributive HENs. This technique distributively stores on HENs partial streams of requested videos from clients connected to HENs and the order of store streams follows the order of request of identical video items from HENs. Thus, storing streams on each HEN that requests sevice are different. When a client requests the cached video on some HENs, the HEN that connects him receives streams in the order of store from HENs which stored them and it transmits them to him. These procedures are performed under the control of SA. This technique uses cache replacement algorithm that the combination of LFU, LRU and the last remove for the first stream of videos In order to reduce end-to-end delay.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1189-1202
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• 1999

As compared with VOD data, NOD article data has the following characteristics: it is created at any time, has a short life cycle, is selected as not one article but several articles by a user, and has high access locality in time. Because of these intrinsic features, user access patterns of NOD article data are different from those of VOD. Thus, building NOD system using the existing techniques of VOD system leads to poor performance. In this paper, we analysis the log file of a currently running electronic newspaper, show that the popularity distribution of NOD articles is different from Zipf distribution of VOD data, and suggest a new popularity model of NOD article data MS-Zipf(Multi-Selection Zipf) distribution and its approximate solution. Also we present a life cycle model of NOD article data, which shows changes of popularity over time. Using this life cycle model, we develop LLBF (Largest Life-cycle Based Frequency) prefetching algorithm and analysis he performance by simulation. The developed LLBF algorithm supports the similar level in hit-ratio to the other prefetching algorithms such as LRU(Least Recently Used) etc, while decreasing the number of data replacement in article prefetching and reducing the overhead of the prefetching in system performance. Using the accurate user access patterns of NOD article data, we could analysis correctly the performance of NOD server system and develop the efficient policies in the implementation of NOD server system.

• The KIPS Transactions:PartD
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• v.18D no.1
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• pp.1-8
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• 2011

The cache structure, which is designed for assuring fast accesses to frequently accessed data, resides on the various levels of computer system hierarchies. Many studies on this cache structure have been conducted and thus many page-replacement algorithms have been proposed. Most of page-replacement algorithms are designed on the basis of heuristic methods by using their own criteria such as how recently pages are accessed and how often they are accessed. This data-retrieval process in computer systems is analogous to human memory retrieval process since the retrieval process of human memory depends on frequency and recency of the retrieval events as well. A recent study regarding human memory cognition revealed that the possibility of the retrieval success and the retrieval latency have a strong correlation with the frequency and recency of the previous retrieval events. In this paper, we propose a novel page-replacement algorithm by utilizing the knowledge from the recent research regarding human memory cognition. Through a set of experiments, we demonstrated that our new method presents better hit-ratio than the LRFU algorithm which has been known as the best performing page-replacement algorithm for DBMS caches.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.224-240
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• 1996

It is common sense for at least one or more levels of cache memory to be used in these day's computer systems. In this paper, the impact of the internal cache memory organization on the performance of the computer is investigated by using a simulator program, which is wirtten by authors and run on SUN SPARC workstation, with several real execution, with several real execution trace files. 280 cache organizations have been simulated using n-way set associative mapping and LRU(Least Recently Used) replacement algorithm with write allocation policy. As a result, 16-way setassociative cache is the best configuration, and when we select 256KB cache memory and 64 byte line size, the bus traffic ratio was decreased compared to that of the noncache system so that a single bus could support almost 7 processors without any delay and degradationof high ratio(hit ratio was 99.21%). The smaller the line size we choose, the little lower hit ratio we can get, but the more processors can be supported by a single bus(maximum 18 processors). Therefore, using a proper cache memory organization can make a single bus structure be able to support multiple processors without any performance degradation.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.3
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• pp.59-66
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• 2020

Content Centric Network(CCN) with architecture that is completely different from traditional host-based networks has emerged to address problems such as the explosion of traffic load in the current network. Research on cache replacement policies is very active to improve the performance of CCN with the characteristics that all routers cache on the network. Therefore, this paper proposes a cache replacement policy suitable for situations in which popularity is constantly changing, taking into account the actual network situation. In order to evaluate the performance of the proposed algorithm, we experimented in an environment where the popularity of content is constantly changing, and confirmed that we are superior to the existing replacement policy through comparing hit rates and analyzing server load.