• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1988.10a
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• pp.79-81
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• 1988

The capacitance-voltage (C-V) characteristics of poly-Si gate MOS devices fabricated by Low-Pressure Chemical Vapor Deposition (LPCVD) system have been studied. In the case poly-Si gate, work function difference and surface state charge density was found lower than that of Al gate. This fact was identified from the C-V curves that flatband shift was shown small due to the hydrogen gas diffused into oxide in processing of alloy and the annealing effect in processing of poly-Si deposition.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.537-538
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• 2010

• Transactions on Electrical and Electronic Materials
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• v.6 no.6
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• pp.245-248
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• 2005

The physical and electrical properties of polycrystalline $\beta$-SiC were studied according to different nitrogen doping concentration. Nitrogen-doped SiC films were deposited by LPCVD(1ow pressure chemical vapor deposition) at $900^{\circ}C$ and 2 torr using $100\%\;H_2SiCl_2$ (35 sccm) and $5 \%\;C_2H_2$ in $H_2$(180 sccm) as the Si and C precursors, and $1\%\;NH_3$ in $H_2$(20-100 sccm) as the dopant source gas. The resistivity of SiC films decreased from $1.466{\Omega}{\cdot}cm$ with $NH_3$ of 20 sccm to $0.0358{\Omega}{\cdot}cm$ with 100 sccm. The surface roughness and crystalline structure of $\beta$-SiC did not depend upon the dopant concentration. The average surface roughness for each sample 19-21 nm and the average surface grain size is 165 nm. The peaks of SiC(111), SiC(220), SiC(311) and SiC(222) appeared in polycrystalline $\beta$-SiC films deposited on $Si/SiO_2$ substrate in XRD(X-ray diffraction) analysis. Resistance of nitrogen-doped SiC films decreased with increasing temperature. The variation of resistance ratio is much bigger in low doping, but the linearity of temperature dependent resistance variation is better in high doping. In case of SiC films deposited with 20 sccm and 100 sccm of $1\%\;NH_3$, the average of TCR(temperature coefficient of resistance) is -3456.1 ppm/$^{\circ}C$ and -1171.5 ppm/$^{\circ}C$, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.12 no.1
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• pp.18-26
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• 1999

In this study, the undoped amorphous layers and phosphorus doped amorphous layers are fabricated using LPCVD at 531$^{\circ}C$ with SiH$_4$ gas or at same temperature with PH$_3$ gas during deposition, respectively. The thickness of deposited amorphous layer from this experiments was 5000 ${\AA}$. In this experiments, undoped amorphous layers are deposited with SiH$_4$and Si$_2$H$\_$6/ gas in a low pressure reactor using LPCVD. These amorphous layers can be doped for poly-silicon by phosphorus ion implantation. The experiments of this study are carried out by phosphorus ion implantation with energy 40 keV into P doped and undoped amorphous silicon layers. The distribution of phosphorus profiles are measured by SIMS(Cameca 6f). Recoiling effects and two dimensional profiles are also explained by comparisions of experimental and simulated data. Finally range moments of SIMS profiles are calculated and compared with simulation results.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.339-343
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• 1999

This paper reports the characteristics of poly-Si TFT unitary CMOS circuits fabricated with various techniques, in order to investigate the optimum process conditions. The active films were deposited by PECVD and LPCVD using $SiH_4\; and\; Si_2H_6$ as source gas, and annealed by SPC and ELA methods. The impurity doping of the oource and drain electrodes was performed by ion implantation and ion shower. In order to investigate the AC characteristics of the poly-Si TFTs processed with various methods, we have examined the current driving characteristics of the polt-Si TFT and the frequency characteristics of 23-stage CMOS ring oscillators. Ithas been observed that the circuits fabricated using $Si_2H_6$ with low-temperature process of ELA exhibit high switching speed and current driving performances, thus suitable for real application of large area electronics.

• Journal of the Korean Vacuum Society
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• v.4 no.3
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• pp.293-300
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• 1995

p-doped poly-Si/SiO2/Si 기판위에 저압 화학증착법(LPCVD)으로 증착한 텅스텐 실리사이드(WS2.7)막을$ 850^{\circ}C$에서 20분 동안 N2 분위기에서 열처리한 후에 건식 분위기에서 열산화하였다. 다결정 실리콘의 인도핑(doping)레벨에 따른 텅스텐 폴리사이드(WSi2.5/poly-Si)막의 산화 성장률과 텅스텐 폴리사이드막의 산화 메카니즘에 대하여 연구하였다. 텅스텐 폴리사이드막의 산화 성장률은 다결정 실리콘의 인(p) 도핑 레벨이 증가함에 따라 증가하였다. 텅스텐 폴리사이드막의 산화는 텅스텐 실리사이드층의 과잉(excess)Si가 초기 산화과정 동안 소모된 후에 다결정 실리콘층의 Si가 소모되었다. 산화막과 산화막을 식각(etching)한 후에 텅스텐 실리사이드막의 표면 거칠기는 다결정 실리？의 인 농도가 적을수록 평탄하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.545-545
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• 2008

Poly-Si is an essential material for floating gate in NAND Flash memory. To fabricate this material within region of floating gate, chemical mechanical polishing (CMP) is commonly used process for manufacturing NAND flash memory. We use colloidal silica abrasive with alkaline agent, polymeric additive and organic surfactant to obtain high Poly-Si to SiO2 film selectivity and reduce surface defect in Poly-Si CMP. We already studied about the effects of alkaline agent and polymeric additive. But the effect of organic surfactant in Poly-Si CMP is not clearly defined. So we will examine the function of organic surfactant in Poly-Si CMP with concentration separation test. We expect that surface roughness will be improved with the addition of organic surfactant as the case of wafering CMP. Poly-Si wafer are deposited by low pressure chemical vapor deposition (LPCVD) and oxide film are prepared by the method of plasma-enhanced tetra ethyl ortho silicate (PETEOS). The polishing test will be performed by a Strasbaugh 6EC polisher with an IC1000/Suba IV stacked pad and the pad will be conditioned by ex situ diamond disk. And the thickness difference of wafer between before and after polishing test will be measured by Ellipsometer and Nanospec. The roughness of Poly-Si film will be analyzed by atomic force microscope.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.4
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• pp.255-260
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• 1998

Behavior of solid phase crystallizations (SPC) of RF sputtered and LPCVD amorphous hydrogenated silicon film were investigated. LPCVD films showed the higher degree of crystallinity and larger grain size than sputtered films. The applicable degree of crystallinity was also obtained from sputtered films. The deposition method of amorphous silicon film influenced the behavior of post annealing SPC. Observed degree of crystallinity of sputtered films strongly depended on the partial pressure of hydrogen in deposition. The higher deposition temperature of sputtering provided the better crystallinity after SPC. Due to the high degree of poly-crystallinity, the retardation of larger grain growth was observed on sputtering film.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.51-58
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• 1993

N-channel TFTs fabricated on the pre-amorphized (by Si ion implantation) and recrystallized Si film having 10.1V threshold voltage, 20.7cm$^{2}$/V$\cdot$s field effect mobility and ~10$^{5}$/ ON/OFF ratio, whowed improved characteristics comparing to those obtained from the as-deposited (by LPCVD) poly Si film which had 11.2V, 9cm$^{2}$/V$\cdot$s and ~10$^{4}$ respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.126-134
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• 1996

Tungsten silicide films were deposited on the phosphorus-doped poly-Si/SiO$_{2}$/Si-substrates by LPCVD (low pressue chemical vapor deposition). The formation and various properties of tungsten silicide processed by furnace annealing in N$_{2}$ ambient were evaluated by using XRD. AFM, 4-point probe and SEM. And the redistribution of phosphorus atoms has been observed by SIMS. The crystal structure of the as-deposited tungsten silicide films were transformed from the hexagonal to the tetragonal structure upon annealing at 550.deg. C. The surface roughness of tungsten polycide films were found to very smoothly upon annelaing at 850.deg. C and low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide films are measured to be 2.4 .ohm./ㅁafter furnace annealing at 1100.deg. C, 30min. It was found that the sheet resistance of tungsten polycide films upon annealing above 1050.deg. C were independant on the phosphorus concentration of polysilicon layer and furnace annealing times. An out-diffusion of phosphorus impurity through tungsten silicide film after annealing in $O_{2}$ ambient revealed a remarkably low content of dopant by oxide capping.