• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.79-86
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• 2020

In this paper, we analyzed the case vulnerable to the power analysis attack of the ARIA algorithm and AES algorithm. Through this, we propose an algorithm with a safe structure for power analysis and prove through experiment. The proposed technique is a masking method using LFSR with a cyclic structure. To verify this, 1000, 2000, and 4000 power traces were collected, and the corresponding results are shown and proved. We used ATmega328 Chip for Arduino Uno for the experiment and mounted each algorithm. In order to measure the power consumption, a resistor was inserted and then proceeded. The analysis results show that the proposed structure has a safe structure for power analysis. In the future, we will study ways to lead to performance enhancement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.7-14
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• 2005

This paper presents a new low power BIST TPG scheme. It uses a transition monitoring window (TMW) that is comprised of a transition monitoring window block and a MUX. When random test patterns are generated by an LFSR, transitions of those patterns satisfy pseudo-random gaussian distribution. The Proposed technique represses transitions of patterns using a k-value which is a standard that is obtained from the distribution of U to observe over transitive patterns causing high power dissipation in a scan chain. Experimental results show that the Proposed BIST TPG schemes can reduce scan transition by about $60\%$ without performance loss in ISCAS'89 benchmark circuits that have large number scan inputs.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.333-340
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• 2018

This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.6
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• pp.673-679
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• 2014

The important requirements of designing a pattern classifier are high throughput and low memory requirements, and low cost hardware implementation. A pattern classifier by using Multiple Attractor Cellular Automata(MACA) proposed by Maji et al. reduced the complexity of the classification algorithm from $O(n^3)$ to O(n) by using Dependency Vector(DV) and Dependency String(DS). In this paper, we generate a pattern classifier using LFSR to improve efficiently the space and time complexity and we propose a method for finding DV by using the 0-basic path. Also we investigate DV and the attractor of the generated pattern classifier. We can divide an n-bit DS by m number of $DV_i$ s and generate various pattern classifiers.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.2
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• pp.25-32
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• 2006

In this paper, we propose a fast correlation attack on the shrinking and self-shrinking generator. This attack is an improved algorithm or the fast correlation attack by Zhang et al. at CT-RSA 2005. For the shrinking generator, we recover the initial state of generating LFSR whose length is 61 with $2^{15.43}$ keystream bits, the computational complexity of $2^{56.3314}$ and success probability 99.9%. We also recover the initial state of generating LFSR whose length is $2^{40}$ of the self-shrinking generator with $2^{45.89}$ keystream bits, the computational complexity of $2^{112.424}$ and success probability 99.9%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6C
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• pp.648-658
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• 2003

As the usage of image/video contents increase, a security problem for the payed image data or the ones requiring confidentiality is raised. This paper proposed an image encryption methodology to hide the image information. The target data of it is the result from quantization in wavelet domain. This method encrypts only part of the image data rather than the whole data of the original image, in which three types of data selection methodologies were involved. First, by using the fact that the wavelet transform decomposes the original image into frequency sub-bands, only some of the frequency sub-bands were included in encryption to make the resulting image unrecognizable. In the data to represent each pixel, only MSBs were taken for encryption. Finally, pixels to be encrypted in a specific sub-band were selected randomly by using LFSR(Linear Feedback Shift Register). Part of the key for encryption was used for the seed value of LFSR and in selecting the parallel output bits of the LFSR for random selection so that the strength of encryption algorithm increased. The experiments have been performed with the proposed methods implemented in software for about 500 images, from which the result showed that only about 1/1000 amount of data to the original image can obtain the encryption effect not to recognize the original image. Consequently, we are sure that the proposed are efficient image encryption methods to acquire the high encryption effect with small amount of encryption. Also, in this paper, several encryption scheme according to the selection of the sub-bands and the number of bits from LFSR outputs for pixel selection have been proposed, and it has been shown that there exits a relation of trade-off between the execution time and the effect of the encryption. It means that the proposed methods can be selectively used according to the application areas. Also, because the proposed methods are performed in the application layer, they are expected to be a good solution for the end-to-end security problem, which is appearing as one of the important problems in the networks with both wired and wireless sections.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.5
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• pp.167-174
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• 2002

This paper analyzes the characteristics of three multipliers and squarers in finite fields GF(2/sup m/) from the point of view of processing time and area complexity. First, we analyze structures of three multipliers and squarers: 1) Systolic array structure, 2), LFSR structure, and 3) CA structure. To make performance analysis, each multiplier and squarer was modeled in VHDL and was synthesized for FPGA implementation. The simulation results show that CA structure is the best from the point view of processing time, and LFSR structure is the best from the point of view of area complexity.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.93-98
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• 2003

This paper presents two new algorithms and their architectures for $AB^2 $ multiplication over $GF(2^m)$.First, a new architecture with a new algorithm is designed based on LFSR (Linear Feedback Shift Register) architecture. Furthermore, modified $AB^2 $ multiplier is derived from the multiplier. The multipliers and the structure use AOP (All One Polynomial) as a modulus, which hat the properties of ail coefficients with 1. Simulation results thews that proposed architecture has lower hardware complexity than previous architectures. They could be. Therefore it is useful for implementing the exponential ion architecture, which is the tore operation In public-key cryptosystems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.610-618
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• 2003

Recently, many deterministic built-in self-test schemes to reduce test time have been researched. These schemes can achieve a good quality test by shortening the whole test process, but require complex algorithms or much hardware. In this paper, a new deterministic BIST scheme is provided that reduces the additional hardware requirements, as well as keeping test time to a minimum. The proposed BIST (Built-In Self-Test) methodology brings about the reduction of the hardware requirements for pseudo-random tests as well. Theoretical study demonstrates the possibility of reducing the hardware requirements for both pseudo-random and deterministic tests, with some explanations and examples. Experimental results show that in the proposed test scheme the hardware requirements for the pseudo-random test and deterministic test are less than in previous research.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.2
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• pp.37-44
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• 2001

In this paper, an efficient architecture for the ECC multiplier in GF(2") is proposed. We give a design example for the irreducible trinomials $x_{193}\;+\;x_{15}\;+\;1$. In hardware implementations, it is often desirable to use the irreducible trinomial equations. A digit-serial multiplier with a digit size of 32 is proposed, which has more advantages than the 193bit serial LFSR architecture. The proposed multiplier is verified with a VHDL description using an elliptic curve addition. The elliptic curve used in this implementation is defined by Weierstrass equations. The measured results show that the proposed multiplier it 0.3 times smaller than the bit-serial LFSR multiplier.lier.