• Journal of Digital Policy
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• v.1 no.2
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• pp.61-69
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• 2022

The paper is a study to develop and verify a blood glucose level prediction model based on biosignals obtained from photoplethysmography (PPG) sensors, ICT technology and data. Blood glucose prediction used the MLP architecture of machine learning. The input layer of the machine learning model consists of 10 input nodes and 5 hidden layers: heart rate, heart rate variability, age, gender, VLF, LF, HF, SDNN, RMSSD, and PNN50. The results of the predictive model are MSE=0.0724, MAE=1.1022 and RMSE=1.0285, and the coefficient of determination (R²) is 0.9985. A blood glucose prediction model using bio-signal data collected from digital devices and machine learning was established and verified. If research to standardize and increase accuracy of machine learning datasets for various digital devices continues, it could be an alternative method for individual blood glucose management.

• Journal of information and communication convergence engineering
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• v.4 no.4
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• pp.170-173
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• 2006

Recently, with increasing efficiency of DSC (photo-electrochemical using a nano-particle), The Performance of DSC solar generation system also needs improvement. The approach consists of a Fly-back DC-DC (transfer ratio 1:10) converter to boost the DSC cell voltage to 300VDC. The four switch (MOSFET) inverter is employed to produce 220V, 60Hz AC outputs. High performance, easy manufacturability, lower component count., safety and cost are addressed. Protection and diagnostic features form an important part of the design. Another highlight of the proposed design is the control strategy, which allows the inverter to adapt to the: requirements of the load as well as the power source. A unique aspect of the design is the use of the DSP TMS320LF2406 to control the inverter by current and voltage feed-back. Efficient and smooth control of the: power drawn from the DSC Cell is achieved by controlling the front end DC-DC converter in current mode.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.582-586
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• 2005

This paper presents a new structure of Phase Locked Loop(PLL) which changes its loop bandwidth according to the locking status. The proposed PLL consists of a conventional PLL and, Locking Status Indicator(LSI). The LSI decides the operating bandwidth of loop filler. When the PLL becomes out of lock, the PLL increases the loop bandwidth and achieves fast locking. When the PLL becomes in-lock, this PLL decreases the loop bandwidth and minimizes phase noise output. The PLL can achieve fast locking and low phase noise output at the same time. Proposed PLL's locking time is less than $40{\mu}s$ and spur is 76.1dBc. It is simulated by HSPICE in a Hynix CMOS $0.35{\mu}m$ Process.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.6
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• pp.811-817
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• 2013

In this study we present a system for pulse-rate period detection and human sensibility evaluation based on the wireless medical telemetry service (WMTS) used for transmission of data from medical telemetry devices to various medical facilities and services. We develop a medical-purpose specific WMTS communication module to transmit biometric signals. From the pulse rate variability(PRV) signal, we attempt to classify positive and negative emotional states based on analysis of the ratio of LF/HF in the frequency domain. We measure the data reception rate according to distance in order to test the performance of the WMTS module and analyze the effects on human sensibility evaluation.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.2
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• pp.161-166
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• 2014

This Electromagnetic metal piece detection sensor, having high sensitivity even under high humidity and dust density, using LVDT was investigated. Metal detection characteristics using phase detection method, for 3 frequencies covering ELF and LF band, were experimentally measured. It was found that the sensitivity for metal and animal food, in which metal piece was included, was exponentially increased as frequency increased. Reducing cutoff frequency of LPF after PD was found to be effective to proportionally increase sensitivity. Also the sensitivity of metal piece detection was enhanced by optimizing BPF bandwidth and SNR. Metal piece detection limit using available ferrous test samples was found to be 0.7mm diameter from the experiment using 50kHz, in ELF band, which was known to have better selectivity to animal food. is an example of ABSTRACT format.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.33 no.1
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• pp.108-113
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• 2010

The purpose of this study was to investigate the differences of driving performance and physiological responses between young male and female drivers for unexpected situation using a graphic vehicle simulator. The participants included 20 college graduates; 23 males aged $24.3\;{\pm}\;1.4$ with $2.3\;{\pm}\;1.5$ years of driving experiences and 23 females aged $23.2\;{\pm}\;2.1$ with $2.2\;{\pm}\;1.7$ years of driving experience. The participants were instructed to drive the vehicle simulator which was programed unexpected situation for two minutes. The physiological measurements used were autonomic responses of electrocardiogram (ECG) and skin conductance response (SCR), and the driving performance measurements used were the reaction time of break and the rate of collision for unexpected situation. Results showed that there were no significant differences between male and female drivers in the reaction time of break and the rate of collision for unexpected situation. Averaged R-R interval decreased and LF IHF and SCL amplitude increased for unexpected situation. There were no significant differences between male and female in the averaged R-R interval and LF/HF for unexpected situation. On the other hand, SCL amplitude of female was higher than male. Rising time to maximum SCL amplitude of female was longer than male.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.45-50
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• 2016

This paper reports a Ringer's solution detector and transceiver design for the efficient management of patients. The ringer's solution detection and transceiver consisted of the main control part, ringer's solution detection part, display and warning light part, wireless transceiver, and power supply part. The light receiving part of the ringer's solution detection part employed TSL260R-LF photodiode; light permeating part, Water-Clear type LED; and wireless transceiver part, the RF wireless data transceiver module, NR-FPCX. As a result of this Ringer's solution detector and transceiver design that can manage the patient efficiently, it was found that when the ringer's solution was detected by the double photodiode, the operating frequency was 11.95kHz; when it was not detected, the number was 9.6kHz. In the ringer's solution receiver, when the ringer's solution was detected, the number was 0. The corresponding unique RF code was displayed when not detected. The power used in the ringer's solution detection part was converted to the Sleep mode to operate under battery save mode. The ringer's solution transceiver can exchange wireless communication approximately within a 700m radius.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.6
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• pp.1419-1435
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• 2015

In this study an active RFID system of low power consumption is proposed, for which we improved the tag collection algorithm of ISO/IEC 18000-7 standard and significantly reduced the tag collection time. We classified the type of power consumption according to the operating mode of active RFID and proposed the method which can accurately estimate battery life time. By calculating the power consumptions of proposed and current methods, we can compare the battery life times of both methods. Through this analysis we can demonstrate the superiority of the proposed method in battery life time.