• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.07a
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• pp.268-271
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• 2011

본 논문에서는 지상파 3D HDTV 방송 서비스를 제공하기 위하여 기존의 유럽형 HDTV 방송 서비스인 DVB-T2 전송 시스템의 채널 부호군을 연구하고, 이 시스템의 외부 부호(Outer Code)로 쓰이는 BCH 부호의 경판정(Hard Decision)을 통한 복호를 연판정(Soft Decision)을 통한 복호로 수정함으로써 성능에 미치는 영향에 대해 살펴보았다. 또한 기존의 DVB-T2 전송시스템의 성능을 살펴보고, 이를 바탕으로 기존의 외부 부호(Outer Code)인 BCH 부호와 내부 부호(Inner Code)인 LDPC 부호의 조합을 연판정이 가능하고 복호하는 블록(Block)의 길이가 더 짧아진 BTC(Block Turbo Code)부호와 LDPC 부호와의 조합으로 바꿈으로써 기존의 DVB-T2 전송 시스템보다 블록 오류율이 낮아짐을 확인하였다.

• Journal of Korea Multimedia Society
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• v.9 no.6
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• pp.728-734
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• 2006

Carrier interferometry code is considered as a promising scheme that provides significant performance improvement via frequency diversity effect. Space-time coding is commonly employed to achieve a performance gain through space diversity. The combination of these techniques and forward error correction coding will lead to enhanced system capacity and performance. This paper presents a low-density parity check (LDPC) coded space-time orthogonal frequency division multiplexing (OFDM) transmission scheme with carrier interferometry code for high-capacity and high-performance mobile multimedia communications. Computer simulations demonstrate that the proposed mobile multimedia transmission system offers a considerable performance improvement of approximately 9dB in terms of Eb/No in the Rayleigh fading channel with relatively low delay spread, in comparison with space-time OFDM. Performance gains are further increased, comparing with traditional OFDM systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2029-2035
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• 2013

In this paper, we presented non-uniform quantization method for LDPC decoder specified in DVB-S2 standard. There are some problems in order to implement LDPC decoder in aspect to algorithm and implementation. In algorithm aspect, because of large number of iterations, LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. Therefore, this paper studies Horizontal Shuffle Scheduling (HSS) algorithm which reduced iteration number without performance loss. In aspect of implementation, there are some solutions to improve the decoding speed, however this paper focused on non-uniform quantization which reduce the quantization bits of LDPC decoder. In simulation results, Decoding throughput of HSS LDPC decoder based on non-uniform quantization is 816Mbps and it improved 12% compared to conventional one.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.104-113
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• 2013

A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.3
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• pp.51-56
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• 2005

To improve the BER of OFDM on a fading channel, a low-density parity check coded OFDM system is proposed in this paper. LDPC codes are decoded with Sum-Product or Belief Propagation Algorithm known by probability propagation algorithm. When LDPC codes are applied to OFDM system, the BER performance is dependant on the iteration number of decoding. To improve the spectral efficiency, multi-level modulations are used in mobile communication system. But, It is not clear how to decode LDPC code used in OFDM with multi-level modulations. In the paper, a decoding algorithm is described for LDPC coded OFDM with MPSK. When use the proposed decoding algorithm, we get the good BER for AWGN and a Fading Channel. Simulation results show that the proposed decoding algorithm is confirmed LDPC coded OFDM with MPSK.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.659-665
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• 2015

Recent studies on network coding scheme for increasing transmission efficiency of the network has been actively conducted. In this paper, we apply RLNC in sub-packet unit and propose a joint scheme of sub-packet level network coding and LDPC code. The proposed method can have similar ability of network coding and obtain further error correction capability. The simulation results show that the proposed one enhances error correction capability compared to the case using only LDPC when extra packets are received.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1892-1897
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• 2012

In this paper, efficient CNU(Check Node Update) algorithms are analyzed for high speed LDPC decoding in DVB-S2 standard. In aspect to CNU methods, there are some kinds of CNU methods. Among of them, MP (Min Product) method is quite often used in LDPC decoding. However MP needs LUT (Look Up Table) that is critical path in LDPC decoding speed. A new SC-NMS (Self-Corrected Normalized Min-Sum) method is proposed in the paper. NMS needs only normalized scaling factor instead of LUT and compensates the overestimation of MP approximation. In addition, SC method is proposed. It gives a faster convergence toward a decoded codeword. If a message change its sign between two iterations, it is not reliable and to avoid to propagate noisy information, its module is set to 0. The performance of SC-NMS has a little degrade compare to MP by 0.1 dB, however considering computational complexity and decoding speed, SC-NMS algorithm is optimal method for CNU algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.801-809
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• 2007

LDPC Low Density Parity Check) code, which is an error correcting code determined to be applied to the 4th generation mobile communication systems, requires a heavy computational complexity due to iterative decodings to achieve a high BER performance. This paper proposes an algorithm to reduce the number of decoding iterations to increase performance of the decoder in decoding latency and power consumption. Measuring changes between the current decoded LLR values and previous ones, the proposed algorithm predicts directions of the value changes. Based on the prediction, the algorithm inverts the sign bits of the LLR values to speed up convergence, which means parity check equation is satisfied. Simulation results show that the number of iterations has been reduced by about 33% without BER performance degradation in the proposed decoder, and the power consumption has also been decreased in proportional to the amount of the reduced decoding iterations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1006-1013
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• 2008

CZZ (Concatenated Zigzag) Code is a class of fast encodable LDPC codes. In the case that LDPC codes including CZZ codes have short length, short cycles seriously affect the code performance. In this paper, we construct CZZ codes using various degree-2 polynomial interleavers which eliminate cycles of length 4 and through simulation, compare the performance of these CZZ codes and turbo codes in many different fading channels. Especially, quasi-static fading channel, block fading channel, uncorrelated fading channel, and correlated fading channel are considered. Since CZZ codes show similar performance as turbo codes, they can be used in the next generation wireless communication systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.