• Title/Summary/Keyword: LDPC Code

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An LDPC Code Replication Scheme Suitable for Cloud Computing (클라우드 컴퓨팅에 적합한 LDPC 부호 복제 기법)

  • Kim, Se-Hoe;Lee, Won-Joo;Jeon, Chang-Ho
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.49 no.2
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    • pp.134-142
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    • 2012
  • This paper analyze an LDPC code replication method suitable for cloud computing. First, we determine the number of blocks suitable for cloud computing through analysis of the performance for the file availability and storage overhead. Also we determine the type of LDPC code appropriate for cloud computing through the performance for three types of LDPC codes. Finally we present the graph random generation method and the comparing method of each generated LDPC code's performance by the iterative decoding process. By the simulation, we confirmed the best graph's regularity is left-regular or least left-regular. Also, we confirmed the best graph's total number of edges are minimum value or near the minimum value.

SISO-RLL Decoding Algorithm of 17PP Modulation Code for High Density Optical Recording Channel (고밀도 광 기록 채널에서 17PP 변조 부호의 연판정 입력 연판정 출력 런-길이 제한 복호 알고리즘)

  • Lee, Bong-Il;Lee, Jae-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.2C
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    • pp.175-180
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    • 2009
  • When we apply the LDPC code for high density optical storage channel, it is necessary to make an algorithm that the modulation code decoder must feed the LDPC decoder soft-valued information because LDPC decoder exploits soft values using the soft input. Therefore, we propose the soft-input soft-output run-length limited 17PP decoding algorithm and compare performance of LDPC codes. Consequently, we found that the proposed soft-input soft-output decoding algorithm using 17PP is 0.8dB better than the soft-input soft-output decoding algorithm using (1, 7) RLL.

Design and Performance Evaluation of Improved Turbo Equalizer (개선된 터보 등화기의 설계와 성능 평가)

  • An, Changyoung;Ryu, Heung-Gyoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.28-38
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    • 2013
  • In this paper, we propose a improved turbo equalizer which generates a feedback signal through a simple calculation to improve performance in single carrier system with the LMS(least mean square) algorithm based equalizer and LDPC(low density parity check) codes. LDPC codes can approach the Shannon limit performance closely. However, computational complexity of LDPC codes is greatly increased by increasing the repetition of the LDPC codes and using a long parity check matrix in harsh environments. Turbo equalization based on LDPC code is used for improvement of system performance. In this system, there is a disadvantage of very large amount of computation due to the increase of the repetition number. To less down the amount of this complicated calculation, The proposed improved turbo equalizer adjusts the adoptive equalizer after the soft decision and the LDPC code. Through the simulation results, it's confirmed that performance of improved turbo equalizer is close to the SISO-MMSE(soft input soft output minimum mean square error) turbo equalizer based on LDPC code with the smaller amount of calculation.

Performance and Iteration Number Statistics of Flexible Low Density Parity Check Codes (가변 LDPC 부호의 성능과 반복횟수 통계)

  • Seo, Young-Dong;Kong, Min-Han;Song, Moon-Kyou
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.1
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    • pp.189-195
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    • 2008
  • The OFDMA Physical layer in the WiMAX standard of IEEE 802.16e adopts 114 LDPC codes with various code rates and block sizes as a channel coding scheme to meet varying channel environments and different requirements for transmission performance. In this paper, the performances of the LDPC codes are evaluated according to various code rates and block-lengths throueh simulation studies using min-sum decoding algorithm in AWGN chamois. As the block-length increases and the code rate decreases, the BER performance improves. In the cases with code rates of 2/3 and 3/4, where two different codes ate specified for each code rate, the codes with code rates of 2/3A and 3/4B outperform those of 2/3B and 3/4A, respectively. Through the statistical analyses of the number of decoding iterations the decoding complexity and the word error rates of LDPC codes are estimated. The results can be used to trade-off between the performance and the complexity in designs of LDPC decoders.

Architecture of an LDPC Decoder for DVB-S2 using reuse Technique of processing units and Memory Relocation (연산기와 메모리 재사용을 이용한 효율적인 DVB-S2 규격의 LDPC 복호기 구조)

  • Park Jae-Geun;Lee Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9 s.351
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    • pp.31-37
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    • 2006
  • Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

Rate-Compatible LDPC Codes Based on the PEG Algorithm for Relay Communication Systems

  • Zhou, Yangzhao;Jiang, Xueqin;Lee, Moon Ho
    • Journal of Communications and Networks
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    • v.17 no.4
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    • pp.346-350
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    • 2015
  • It is known that the progressive edge-growth (PEG) algorithm can be used to construct low-density parity-check (LDPC) codes at finite code lengths with large girths through the establishment of edges between variable and check nodes in an edge-by-edge manner. In [1], the authors derived a class of LDPC codes for relay communication systems by extending the full-diversity root-LDPC code. However, the submatrices of the parity-check matrix H corresponding to this code were constructed separately; thus, the girth of H was not optimized. To solve this problem, this paper proposes a modified PEG algorithm for use in the design of large girth and full-diversity LDPC codes. Simulation results indicated that the LDPC codes constructed using the modified PEG algorithm exhibited a more favorable frame error rate performance than did codes proposed in [1] over block-fading channels.

Split LDPC Codes for Hybrid ARQ

  • Joo, Hyeong-Gun;Hong, Song-Nam;Shin, Dong-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.10C
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    • pp.942-949
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    • 2007
  • In this paper, we propose a new rate-control scheme, called splining, to construct low-rate codes from high-rate codes by splitting rows of the parity-check matrices of LDPC codes, which can construct rate-compatible LDPC codes having good initial transmission performance. Good low-rate codes can be constructed by making the number of distinct check node degrees as small as possible after splitting. The proposed scheme achieves good cycle property, low decoding complexity, and fast convergence speed, especially compared to the puncturing. Especially, rate-compatible repeat accumulate-type LDPC (RA-Type LDPC) code is constructed using splitting, which covers the code rates from 1/3 to 4/5. Through simulation it is shown that this code outperforms other rate-compatible RA-Type LDPC codes for all rates and can be decoded conveniently and efficiently.

Adaptive Decision Feedback Equalizer Based on LDPC Code for the Phase Noise Suppression and Performance Improvement (위상잡음 제거와 성능향상을 위한 LDPC 부호 기반의 적응형 판정 궤환 등화기)

  • Kim, Do-Hoon;Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37 no.3A
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    • pp.179-187
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    • 2012
  • In this paper, we propose an adaptive DFE (Decision Feedback Equalizer) based on LDPC (Low Density Parity Check) code for phase noise suppression and performance improvement. The proposed equalizer in this paper is applied for wireless repeater system. So as to meet ever increasing requirements on higher wireless access data rate and better quality of service (QoS), the wireless repeater system has been studied. The echo channel and RF impairments such as phase noise produce performance degradation. In order to remove echo channel and phase noise, we suggest a novel adaptive DFE equalizer based on LDPC code. The proposed equalizer helps to compensate RF impairments and improve the performance significantly better than used independently. In addition, proposed equalizer has less iteration number of LDPC code. So, the proposed equalizer system has low complexity.

Construction of Semi-Algebra Low Density Parity Check Codes for Parallel Array Processing (병렬 어레이 프로세싱을 위한 반집합 대수 LDPC 부호의 구성)

  • Lee Kwang-jae;Lee Moon-ho;Lee Dong-min
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.1C
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    • pp.1-8
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    • 2005
  • In this paper, we present a novel LDPC code construction called as semi-algebra low density parity check(LDPC) codes which is one kind of deterministic LDPC code based on dual-diagonal sub-matrix. The constructing method results in a class of high rate LDPC codes. Codes in this class have a large girth and good minimum distances. Furthermore, they can be implemented by simple parallel array architecture using cyclic shift register and perform well with the iterative decoding.

LDPC Decoding by Failed Check Nodes for Serial Concatenated Code

  • Yu, Seog Kun;Joo, Eon Kyeong
    • ETRI Journal
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    • v.37 no.1
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    • pp.54-60
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    • 2015
  • The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.