• 대한임베디드공학회논문지
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• 제11권6호
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• pp.325-334
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• 2016

Recently, Open Computing Language (OpenCL) has been proposed to provide a framework that supports heterogeneous computing platforms. By using an OpenCL framework, digital communication systems can support various protocols in a unified computing environment to achieve both high portability and high performance. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes for China Multimedia Mobile Broadcasting (CMMB) on a heterogeneous platform. Each step of LDPC decoding has different parallelization characteristics. In this paper, steps suitable for task-level parallelization are executed on the CPU, and steps suitable for data-level parallelization are processed by the GPU. To improve the performance of the proposed OpenCL kernels for LDPC decoding operations, explicit thread scheduling, loop-unrolling, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance by using heterogeneous multi-core processors on a unified computing framework.

• Journal of Communications and Networks
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• 제14권4호
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• pp.429-433
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• 2012

In this paper, we consider nonbinary quasi-cyclic low-density parity-check (QC-LDPC) codes and propose a method to design multiple rate codes with either fixed information bit length or block bit length, tailored to different scenarios in wireless applications. We show that the proposed codes achieve good performance over a broad range of code rates.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.473-476
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• 2004

Low-Density Parity-Check (LDPC) codes are recently emerged due to its excellent performance to use. However, the parity check matrices (H) of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix for partially parallel decoder structures, which is efficient in hardware implementation of both decoders and encoders. Using proposed methods, the encoding design can become practical while keeping the hardware complexity of partially parallel decoder structures.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• 방송공학회논문지
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• 제15권5호
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• pp.665-671
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• 2010

본 논문에서는 DVB-T2 (digital video broadcasting for terrestrial - 2nd generation) 시스템을 위한 터보 등화기를 제안 하고 그 성능을 분석하였다. 터보 등화기는 MAP (maximum a posteriori) 검파기와 LDPC (low density parity check) 복호기로 구성 되었다. LS(least square) 채널 추정 기반 SISO (soft-input-soft-output) MAP 등화기는 LDPC 복호기에 외래 확률 값을 준다. 터보 등화기의 성능을 반복 횟수에 따라 컴퓨터 실험을 통하여 분석하였다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.415-418
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• 2011

WiMAX, WLAN 등의 무선통신 시스템에 사용되는 LDPC(low-density parity check) 복호기의 핵심 기능블록인 DFU(decoding function unit)의 회로 최적화를 제안한다. 최소합(min-sum) 복호 알고리듬 기반의 DFU는 2의 보수 값과 sign-magnitude 값 사이의 변환이 필요하여 회로가 복잡해진다. 본 논문에서는 sign-magnitude 연산 기반의 DFU를 설계하여 수체계 변환과정을 제거함으로써 회로를 간소화시키고 동작속도를 향상시켰다.

• 한국정보전자통신기술학회논문지
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• 제17권4호
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• pp.198-204
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• 2024

항공 우주 분야의 데이터 전송 방식의 표준인 IRIG 106 표준에서 오류 정정 능력이 뛰어난 LDPC가 채널 부호화 기법으로 채택되었다. LDPC와 같은 반복 부호는 큰 블록 크기와 많은 반복 횟수를 필요하고 이로 인해 계산량과 전력 소모가 늘어나는 결과를 초래한다. 이러한 문제점을 개선하고자 본 논문에서는 IRIG 106 표준에 따른 정보비트 크기와 부호화율에 대해 동일한 성능을 유지하면서 평균 반복 횟수를 감소하는 parity check 방식 기반의 조기 종료 알고리즘을 제시하였다. 기존 방식과 성능 및 반복 감소 정도를 비교 분석하였으며. 각 부호화 별 동일 성능을 유지하면서 반복 횟수가 약 50% 이상 감소됨을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.999-1000
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• 2006

The LDPC Code is focusing a powerful FEC(Forward Error Correction) codes for 4G Mobile Communication system. LDPC codes are used minimizing channel errors by modeling AWGN Channel as VDSL system. The performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. LDPC code are encoded by sparse parity check matrix. there are decoding algorithms for a LDPC code, Bit Flipping, Message passing, Sum-Product. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten.

• Journal of Electrical Engineering and Technology
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• 제12권3호
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• pp.1262-1270
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• 2017

Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.

• 한국통신학회논문지
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• 제32권9C호
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• pp.801-809
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• 2007

LDPC 부호는 4G 이동통신 시스템에 적합한 오류 정정 부호이다. 그러나 알고리듬의 특성상 좋은 BER 성능을 위해서는 반복 복호에 의한 많은 연산량이 요구된다. 본 논문에서는 복호지연과 전력 소모에 대한 복호기의 성능을 증가시키기 위하여 반복 복호 횟수를 줄이는 알고리듬에 대하여 제안한다. 제안된 알고리듬은 현재 LLR 복호값과 이전 LLR 복호값 사이의 변화를 측정하고 변화 방향을 예측하며, 패리티 검사식을 만족시켜 수렴속도를 높이도록 LLR 값의 sign 비트를 반전시킨다. 실험결과, 제안한 방법은 BER 성능의 감소 없이 반복 복호 횟수를 약 33% 정도 줄이는 것이 가능하며 감소된 반복 복호 횟수에 비례하여 소모 전력도 감소시킬 수 있다.