• Journal of Convergence for Information Technology
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• v.11 no.6
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• pp.7-13
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• 2021

In this paper, the function of starting the negative voltage used in the IT equipment when it is generated and the method of controlling it using a microcontroller for the function to detect the overload and respond to it are presented. To do this, the limitations of the existing negative voltage generation circuit and the problems that occur during overload were analyzed, and a circuit that detects and controls the overload condition without a separate current sensing circuit was presented. In order to confirm the effect of the proposed method, an experiment was conducted by configuring an experimental circuit. As a result of the experiment, compared to the existing negative voltage generation circuit, which falls into a latch-up state when overloaded and enters a dangerous state, the proposed circuit detects this, stop the operation of the circuit, and informs the user of such an abnormal state to take action. have. In addition, since the starting point of the circuit is determined according to the system state, the experimental result was confirmed that the starting time was significantly shortened by about 23% compared to the time switch method.

• Journal of IKEEE
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• v.25 no.4
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• pp.735-740
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• 2021

In this paper, we propose a new ESD protection device with high holding voltage with low current gain of parasitic NPN BJT by improving the structure of the existing LTDDSCR. The electrical characteristics of the proposed protection device were analyzed by HBM simulation using Synopsys' TCAD simulation, and the operation of the added BJT was confirmed by current flow, impact ionization and recombination simulation. In addition, the holding voltage characteristics were optimized with the design variables D1 and D2. As a result of the simulation, it was verified that the new ESD protection device has a higher holding voltage compared to the existing LTDDSCR and has a symmetrical bidirectional characteristic. Therefore, the proposed ESD protection device has high area efficiency when applied to an IC and is expected to improve the reliability of the IC.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.40 no.1
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• pp.73-79
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• 2016

Higher circuit breaker safety standards can be obtained by increasing the sustaining time of the latching section. This time increase is achieved through velocity reduction after contacting when the closing mechanism operates. The potential for the re-closing phenomenon to occur is also reduced by obtaining time to return open latch. In this study, the sustaining time for the latching section was increased through cam profile optimization based on the displacement response of the moving parts. In addition, the existing performance velocity was also satisfied. A multibody dynamics model of the circuit breaker was developed using ADAMS. To validate the model, simulation results were compared to experiment results. Then, cam profile optimization was carried out using an optimal design program PIAnO. Design variables selected included the radial direction of the cam. Design sensitivity analysis was carried out by design section as well. As a result of optimization, the sustaining time for the latching section was increased.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.9
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• pp.535-540
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• 2017

The changes in the electrical characteristics of CMOS ICs due to coupling with a narrow-band electromagnetic wave were analyzed in this study. A magnetron (3 kW, 2.45 GHz) was used as the narrow-band electromagnetic source. The DUT was a CMOS logic IC and the gate output was in the ON state. The malfunction of the ICs was confirmed by monitoring the variation of the gate output voltage. It was observed that malfunction (self-reset) and destruction of the ICs occurred as the electric field increased. To confirm the variation of electrical characteristics of the ICs due to the narrow-band electromagnetic wave, the pin-to-pin resistances (Vcc-GND, Vcc-Input1, Input1-GND) and input capacitance of the ICs were measured. The pin-to-pin resistances and input capacitance of the ICs before exposure to the narrow-band electromagnetic waves were $8.57M{\Omega}$ (Vcc-GND), $14.14M{\Omega}$ (Vcc-Input1), $18.24M{\Omega}$ (Input1-GND), and 5 pF (input capacitance). The ICs exposed to narrow-band electromagnetic waves showed mostly similar values, but some error values were observed, such as $2.5{\Omega}$, $50M{\Omega}$, or 71 pF. This is attributed to the breakdown of the pn junction when latch-up in CMOS occurred. In order to confirm surface damage of the ICs, the epoxy molding compound was removed and then studied with an optical microscope. In general, there was severe deterioration in the PCB trace. It is considered that the current density of the trace increased due to the electromagnetic wave, resulting in the deterioration of the trace. The results of this study can be applied as basic data for the analysis of the effect of narrow-band high-power electromagnetic waves on ICs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.1-9
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• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.7-17
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• 2010

In this paper, an innovative low-power SRAM based on 4-transistor latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. Moreover, the design reduces the leakage current in the memory cells. The proposed SRAM has been demonstrated through 16-kbit test chip fabricated in a 0.18-${\mu}m$ CMOS process. It shows 17.5 ns access at 1.8-V supply while consuming dynamic power of $87.6\;{\mu}W/MHz$ (for read cycle) and $70.2\;{\mu}W/MHz$ (for write cycle). Compared with those of the conventional 6-transistor SRAM, it exhibits the power reduction of 30 % (read) and 42 % (write) respectively. Silicon measurement also confirms that the proposed SRAM achieves nearly 64 % reduction in the total standby power dissipation. This novel SRAM might be effective in realizing low-power embedded memory in future mobile applications.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.9-15
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• 2003

An optimized finite-field multiplier is proposed for encryption and error correction devices. It is based on a modified Linear Feedback Shift Register (LFSR) which has lower power consumption and smaller area than prior LFSR-based finite-field multipliers. The proposed finite field multiplier for GF(2n) multiplies two n-bit polynomials using polynomial basis to produce $z(x)=a(x)^*b(x)$ mod p(x), where p(x) is a irreducible polynomial for the Galois Field. The LFSR based on a serial multiplication structure has less complex circuits than array structures and hybrid structures. It is efficient to use the LFSR structure for systems with limited area and power consumption. The prior finite-field multipliers need 3${\cdot}$m flip-flops for multiplication of m-bit polynomials. Consequently, they need 6${\cdot}$m latches because one flip-flop consists of two latches. The proposed finite-field multiplier requires only 4${\cdot}$m latches for m-bit multiplication, which results in 1/3 smaller area than the prior finite-field multipliers. As a result, it can be used effectively in encryption and error correction devices with low-power consumption and small area.