• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.4
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• pp.322-329
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• 2012

This paper proposes a non-isolated bidirectional soft-switching converter with high voltage for high step-up/down and high power applications. Compared to the conventional boost converter the proposed converter can achieve approximately doubled voltage gain using the same duty cycle. The voltage ratings of the switch and diode are reduced to half, which result in the use of devices with lower $R_{DS(ON)}$ and on drop leading to reduced conduction losses. Also, voltage ratings of the passive components are reduced, and therefore the total energy volume is reduced to half. Further, the switch is turned on with ZVS in the CCM operation which results in negligible surge caused leading to reduced switching losses. The validity of the proposed converter is proved through a 10kW prototype.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.4
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• pp.273-280
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• 2018

This paper proposes a zero-voltage-transition pulse-width modulation (PWM) DC-DC converter that uses a new active-snubber-cell. The converter main switch can be turned on and off with ZVS, while the snubber switch is turned on with ZCS and turned off with ZVS. Other semiconductor devices are operated under the soft-switching condition. Normal PWM control can be used, the proposed active-snubber-cell does not impose any additional voltage and current stresses. The active-snubber-cell is suitable for high-power applications due to its easy integration into interleaved converters. This paper discusses the operation of the converter, presents some design guidelines, and provides the results of an experiment with a 100 kHz and 1 kW prototype. A peak efficiency of 97.8% is recorded.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.4
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• pp.291-297
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• 2012

Recently, Switching devices become cheaper, depending on the multi-level inverters are considered as the power-conversion systems for high-power and power-quality demanding applications. The multi-level inverters can reduce the THD(Total Harmonic Distortion) as the output which is similar sinusoidal waveform by synthesizing several capacitor DC voltages. However it has some disadvantages such as increased number of components, complex PWM control method. Therefore, this paper is proposed the new multi-level inverter topology using an new H-bridge output stage with a bidirectional auxiliary switch. The proposed topology is the 4-level 3-phase PWM inverter with less switching part than conventional multi-level inverters and reactive power control possible. In order to understand the new multi-level inverter, topology analysis and switching patterns and modes according to the current loop are described in this paper. The proposed multi-level inverter topology is validated through PSIM simulation and the experimental results are provided from a prototype.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.4
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• pp.10-21
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• 2003

Recently, the optical subscriber interface module uses the high performance network processor to quickly develop new application services such as MPLS, VPN, RPR and EPON with a short time-to-market. Although a number of vendors are developing the network processor at 2.5Gbps, only the IBM NP4GS3 can provide packet processing with wire-speed at 2.5Gbps. IBM NP4GS3, however, uses its unique speed DASL interface instead of CSIX-Ll interface, which has standardized by M: Forum currently Therefore, we implement an interconnection mechanism to use the switch fabric with CSIX-Ll interface. In this paper, we suggest the architecture and a packet control mechanism supporting interconnection between IBM NP4GS3 DASL and CSIX-Ll switch interface using the common IBM UDASL ASIC and XILINX FPGA.

• Journal of IKEEE
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• v.14 no.3
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• pp.232-235
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• 2010

A 60GHz active phase shifter with 65nm CMOS is presented by replacing passive switches in switched-line type phase shifter with active ones. Active-switch phase shifter is composed of active-switch blocks and passive delay network blocks. The active-switch phase shifter design is compact compare with the conventional vector-sum phase shifter. Active-switch blocks are designed to accomplish required input and output impedances whose requirements are different whether the switch is on or off. And passive delay network blocks are composed of lumped L,C instead of normal microstrip line to reduce the size of the circuit. An 1-bit phase shifter is fabricated by TSMC 65nm CMOS technology and measurement results present -4dB average insertion loss and 120 degree phase shift at 65GHz.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.4
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• pp.361-370
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• 2006

A single-stage single-switch flyback converter with synchronous rectifier is proposed. The proposed single-stage single-switch technique meets the IEC 61000-3-2 harmonic requirements. The proposed SR is the voltage driven synchronous rectifier (VDSR) which operates depending on the voltage drop across the drain and source of the MOSFET. Experimental results for the 85W (12V /7.1A) proposed converter are shown.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.127-129
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• 2002

NP Forum에서는 다양한 밴더의 네트워크 프로세서와 스위치 패브릭간에 물리적 인터페이스를 제공하기 위해 CSIX-L1(Common Switch Interface-Level 1 )인터페이스를 표준화하였다. IBM 네트워크 프로세서는 MPLS 및 VPN, VLAN, Security, Ipv6와 같은 다양한 어플리케이션과 TBI. SMII CMII. POS bus등 다양한 가입자 인터페이스를 지원하며, L2 기 반에서 2.5Gbps 이상의 패킷 처리를 수행하기 때문에 많은 시스템에 사용된다. 그러나 IBM네트워크 프로세서는 스위치 인터페이스로 DASL인터페이스를 사용한다. 따라서 DASL인 터페이스와 CSIX-L1 인터페이스를 정합하기 위해서는 IBM UDASL칩을 이용해 DASL인 터페이스를 UTOPIA-L3인터페이스로 변환해야 하며, 이것을 다시 CSIX-L1인터페이스로 변환해야 한다. 따라서 본 논문에서는 UTOPIA-L3인터페이스 패킷과 CSIX-L1인터페이스 프레임을 상호 변환하는 모듈을 설계하였으며, 32비트 데이터 버스와 최대 125MHz로클록을 사용해 최대 4Gbps의 패킷처리를 제공하도록 구현하였다. 또한 스위치 패브릭의 특정 포트에서 과잉 트래픽 전달로 인해 발생할 수 있는 블로킹을 방지하기 위해 네트워크 프로세서에게 3개의 Priority／최대 64개 포트수의 VOQ(Virtual Output Queue)를 제공하는 기법에 대해서 기술한다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.4
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• pp.155-159
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• 2004

This paper describes the design and the simulation of a single pole double throw(SPDT) FET switch for wireless LAN(IEEE802.11a ＆ IEEE802.11b) applications using drain impedance transformation network with Microstrip transmission line. At the receiving path insertion losses were from 0.8(㏈) to 1.462(㏈) between 2(㎓) and 4(㎓), from l.26(㏈) to 2.3(㏈) between 4.7(㎓) and 6.7(㎓) and the isolations were under 30(㏈) between 2(㎓) and 6.7(㎓). At the transmitting path insertion loss were from 1.18(㏈) to 2.87(㏈) between 2(㎓) and 4(㎓) from 0.625(㏈) to 1.2(㏈) between 4.7(㎓) and 6.7(㎓) and the isolations were under 30(㏈) between 2(㎓) and 6.7(㎓).

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.3-4
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• 2013

본 논문은 슈퍼커패시터용 양방향 DC-DC 컨버터의 충 방전 시의 스위치 손실 분석을 통한 변압기 권선비 설계에 관한 내용이다. Dual Full-Bridge 방식의 양방향 DC-DC 컨버터의 충 방전 동작분석을 통하여 스위치에서 발생하는 손실을 분석하고 변압기 권선비를 달리하여 각 손실을 비교했을 때 가장 작은 손실을 갖는 변압기 권선비를 파악하여 설계에 반영하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.1217-1219
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• 2003

상용화되어 있는 이동통신 기기의 Front-end 부분은 듀플렉서와 필터를 포함하는 수동소자로 구성되어 있다. 듀플렉서의 임피던스 정합선로는 전송선로 이론으로부터 설계하며, 단순하게 ${\lambda}=1/4$ 파장 길이의 정합 선로를 설치하는 것이기 때문에 정합선로를 이용한 듀플렉서 성능을 극대화하기 위한 설계의 융통성이 없는게 현실이다. 이런 문제점을 해결하기 위하여 집중소자(lumped element)인 R L C를 탄성 표면파 듀플렉서 대신 스위치 모들에 적용하게 된다면 여러 가지 다양한 형태의 회로를 구현할 수 있고 회로망 내에 위치하는 집중소자의 정격을 최적화하여 스위치 모듈의 성능을 향상시킬 수 있는 가능성이 있다. 본 연구에서는 $900 MHz{\sim}2.2 GHz$의 대역에서 소형화 집적화에 적용 가능한 디바이스를 개발하기 위하여 고주파, 저진압, 저손실 스위치 모듈의 제조와 구성되는 커패시터와 인덕터의 제조와 특성에 관하여 연구하였다.