• Title/Summary/Keyword: Key sharing

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Cluster-based Pairwise Key Establishment in Wireless Sensor Networks (센서 네트워크에서의 안전한 통신을 위한 클러스터 기반 키 분배 구조)

  • Chun Eunmi;Doh Inshil;Oh Hayoung;Park Soyoung;Lee Jooyoung;Chae Kijoon;Lee Sang-Ho;Nah Jaehoon
    • The KIPS Transactions:PartC
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    • v.12C no.4 s.100
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    • pp.473-480
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    • 2005
  • We can obtain useful information by deploying large scale sensor networks in various situations. Security is also a major concern in sensor networks, and we need to establish pairwise keys between sensor nodes for secure communication. In this paper, we propose new pairwise key establishment mechanism based on clustering and polynomial sharing. In the mechanism, we divide the network field into clusters, and based on the polynomial-based key distribution mechanism we create bivariate Polynomials and assign unique polynomial to each cluster. Each pair of sensor nodes located in the same cluster can compute their own pairwise keys through assigned polynomial shares from the same polynomial. Also, in our proposed scheme, sensors, which are in each other's transmission range and located in different clusters, can establish path key through their clusterheads. However, path key establishment can increase the network overhead. The number of the path keys and tine for path key establishment of our scheme depend on the number of sensors, cluster size, sensor density and sensor transmission range. The simulation result indicates that these schemes can achieve better performance if suitable conditions are met.

Providing survivability for virtual networks against substrate network failure

  • Wang, Ying;Chen, Qingyun;Li, Wenjing;Qiu, Xuesong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.9
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    • pp.4023-4043
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    • 2016
  • Network virtualization has been regarded as a core attribute of the Future Internet. In a network virtualization environment (NVE), multiple heterogeneous virtual networks can coexist on a shared substrate network. Thus, a substrate network failure may affect multiple virtual networks. In this case, it is increasingly critical to provide survivability for the virtual networks against the substrate network failures. Previous research focused on mechanisms that ensure the resilience of the virtual network. However, the resource efficiency is still important to make the mapping scheme practical. In this paper, we study the survivable virtual network embedding mechanisms against substrate link and node failure from the perspective of improving the resource efficiency. For substrate link survivability, we propose a load-balancing and re-configuration strategy to improve the acceptance ratio and bandwidth utilization ratio. For substrate node survivability, we develop a minimum cost heuristic based on a divided network model and a backup resource cost model, which can both satisfy the location constraints of virtual node and increase the sharing degree of the backup resources. Simulations are conducted to evaluate the performance of the solutions. The proposed load balancing and re-configuration strategy for substrate link survivability outperforms other approaches in terms of acceptance ratio and bandwidth utilization ratio. And the proposed minimum cost heuristic for substrate node survivability gets a good performance in term of acceptance ratio.

A Public-key Cryptography Processor supporting P-224 ECC and 2048-bit RSA (P-224 ECC와 2048-비트 RSA를 지원하는 공개키 암호 프로세서)

  • Sung, Byung-Yoon;Lee, Sang-Hyun;Shin, Kyung-Wook
    • Journal of IKEEE
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    • v.22 no.3
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    • pp.522-531
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    • 2018
  • A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.

Clustering Strategy Based on Graph Method and Power Control for Frequency Resource Management in Femtocell and Macrocell Overlaid System

  • Li, Hongjia;Xu, Xiaodong;Hu, Dan;Tao, Xiaofeng;Zhang, Ping;Ci, Song;Tang, Hui
    • Journal of Communications and Networks
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    • v.13 no.6
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    • pp.664-677
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    • 2011
  • In order to control interference and improve spectrum efficiency in the femtocell and macrocell overlaid system (FMOS), we propose a joint frequency bandwidth dynamic division, clustering and power control algorithm (JFCPA) for orthogonal-frequency-division-multiple access-based downlink FMOS. The overall system bandwidth is divided into three bands, and the macro-cellular coverage is divided into two areas according to the intensity of the interference from the macro base station to the femtocells, which are dynamically determined by using the JFCPA. A cluster is taken as the unit for frequency reuse among femtocells. We map the problem of clustering to the MAX k-CUT problem with the aim of eliminating the inter-femtocell collision interference, which is solved by a graph-based heuristic algorithm. Frequency bandwidth sharing or splitting between the femtocell tier and the macrocell tier is determined by a step-migration-algorithm-based power control. Simulations conducted to demonstrate the effectiveness of our proposed algorithm showed the frequency-reuse probability of the FMOS reuse band above 97.6% and at least 70% of the frequency bandwidth available for the macrocell tier, which means that the co-tier and the cross-tier interference were effectively controlled. Thus, high spectrum efficiency was achieved. The simulation results also clarified that the planning of frequency resource allocation in FMOS should take into account both the spatial density of femtocells and the interference suffered by them. Statistical results from our simulations also provide guidelines for actual FMOS planning.

Design of cellular, satellite, and integrated systems for 5G and beyond

  • Kim, Junhyeong;Casati, Guido;Cassiau, Nicolas;Pietrabissa, Antonio;Giuseppi, Alessandro;Yan, Dong;Strinati, Emilio Calvanese;Thary, Marjorie;He, Danping;Guan, Ke;Chung, Heesang;Kim, Ilgyu
    • ETRI Journal
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    • v.42 no.5
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    • pp.669-685
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    • 2020
  • 5G AgiLe and fLexible integration of SaTellite And cellulaR (5G-ALLSTAR) is a Korea-Europe (KR-EU) collaborative project for developing multi-connectivity (MC) technologies that integrate cellular and satellite networks to provide seamless, reliable, and ubiquitous broadband communication services and improve service continuity for 5G and beyond. The main scope of this project entails the prototype development of a millimeter-wave 5G New Radio (NR)-based cellular system, an investigation of the feasibility of an NR-based satellite system and its integration with cellular systems, and a study of spectrum sharing and interference management techniques for MC. This article reviews recent research activities and presents preliminary results and a plan for the proof of concept (PoC) of three representative use cases (UCs) and one joint KR-EU UC. The feasibility of each UC and superiority of the developed technologies will be validated with key performance indicators using corresponding PoC platforms. The final achievements of the project are expected to eventually contribute to the technical evolution of 5G, which will pave the road for next-generation communications.

De-Centralized Information Flow Control for Cloud Virtual Machines with Blowfish Encryption Algorithm

  • Gurav, Yogesh B.;Patil, Bankat M.
    • International Journal of Computer Science & Network Security
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    • v.21 no.12
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    • pp.235-247
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    • 2021
  • Today, the cloud computing has become a major demand of many organizations. The major reason behind this expansion is due to its cloud's sharing infrastructure with higher computing efficiency, lower cost and higher fle3xibility. But, still the security is being a hurdle that blocks the success of the cloud computing platform. Therefore, a novel Multi-tenant Decentralized Information Flow Control (MT-DIFC) model is introduced in this research work. The proposed system will encapsulate four types of entities: (1) The central authority (CA), (2) The encryption proxy (EP), (3) Cloud server CS and (4) Multi-tenant Cloud virtual machines. Our contribution resides within the encryption proxy (EP). Initially, the trust level of all the users within each of the cloud is computed using the proposed two-stage trust computational model, wherein the user is categorized bas primary and secondary users. The primary and secondary users vary based on the application and data owner's preference. Based on the computed trust level, the access privilege is provided to the cloud users. In EP, the cipher text information flow security strategy is implemented using the blowfish encryption model. For the data encryption as well as decryption, the key generation is the crucial as well as the challenging part. In this research work, a new optimal key generation is carried out within the blowfish encryption Algorithm. In the blowfish encryption Algorithm, both the data encryption as well as decryption is accomplishment using the newly proposed optimal key. The proposed optimal key has been selected using a new Self Improved Cat and Mouse Based Optimizer (SI-CMBO), which has been an advanced version of the standard Cat and Mouse Based Optimizer. The proposed model is validated in terms of encryption time, decryption time, KPA attacks as well.

Verification and Implementation of a Service Bundle Authentication Mechanism in the OSGi Service Platform Environment (OSGi 서비스 플랫폼 환경에서 서비스 번들 인증 메커니즘의 검증 및 구현)

  • 김영갑;문창주;박대하;백두권
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.1_2
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    • pp.27-40
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    • 2004
  • The OSGi service platform has several characteristics as in the followings. First, the service is deployed in the form of self-installable component called service bundle. Second, the service is dynamic according to its life-cycle and has interactions with other services. Third, the system resources of a home gateway are restricted. Due to these characteristics of a home gateway, there are a lot of rooms for malicious services can be Installed, and further, the nature of service can be changed. It is possible for those service bundles to influence badly on service gateways and users. However, there is no service bundle authentication mechanism considering those characteristics for the home gateway In this paper, we propose a service bundle authentication mechanism considering those characteristics for the home gateway environment. We design the mechanism for sharing a key which transports a service bundle safely in bootstrapping step that recognize and initialize equipments. And we propose the service bundle authentication mechanism based on MAC that use a shared secret created in bootstrapping step. Also we verify the safety of key sharing mechanism and service bundle authentication mechanism using a BAN Logic. This service bundle authentication mechanism Is more efficient than PKI-based service bundle authentication mechanism or RSH protocol in the service platform which has restricted resources such as storage spaces and operations.

Listeria monocytogenes Serovar 4a is a Possible Evolutionary Intermediate Between L. monocytogenes Serovars 1/2a and 4b and L. innocua

  • Chen, Jianshun;Jiang, Lingli;Chen, Xueyan;Luo, Xiaokai;Chen, Yang;Yu, Ying;Tian, Guoming;Liu, Dongyou;Fang, Weihuan
    • Journal of Microbiology and Biotechnology
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    • v.19 no.3
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    • pp.238-249
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    • 2009
  • The genus Listeria consists of six closely related species and forms three phylogenetic groups: L. monocytogenes-L. innocua, L. ivanovii-L. seeligeri-L. welshimeri, and L. grayi. In this report, we attempted to examine the evolutionary relationship in the L. monocytogenes-L. innocua group by probing the nucleotide sequences of 23S rRNA and 16S rRNA, and the gene clusters lmo0029-lmo0042, ascB-dapE, rplS-infC, and prs-ldh in L. monocytogenes serovars 1/2a, 4a, and 4b, and L. innocua. Additionally, we assessed the status of L. monocytogenes-specific inlA and inlB genes and 10 L. innocua-specific genes in these species/serovars, together with phenotypic characterization by using in vivo and in vitro procedures. The results indicate that L. monocytogenes serovar 4a strains are genetically similar to L. innocua in the lmo0035-lmo0042, ascB-dapE, and rplS-infC regions and also possess L. innocua-specific genes lin0372 and lin1073. Furthermore, both L. monocytogenes serovar 4a and L. innocua exhibit impaired intercellular spread ability and negligible pathogenicity in mouse model. On the other hand, despite resembling L. monocytogenes serovars 1/2a and 4b in having a nearly identical virulence gene cluster, and inlA and inlB genes, these serovar 4a strains differ from serovars 1/2a and 4b by harboring notably altered actA and plcB genes, displaying strong phospholipase activity and subdued in vivo and in vitro virulence. Thus, by possessing many genes common to L. monocytogenes serovars 1/2a and 4b, and sharing many similar gene deletions with L. innocua, L. monocytogenes serovar 4a represents a possible evolutionary intermediate between L. monocytogenes serovars 1/2a and 4b and L. innocua.

An Inherent Zero-Voltage and Zero-Current-Switching Full-Bridge Converter with No Additional Auxiliary Circuits

  • Wang, Jianhua;Ji, Baojian;Wang, Hongbo;Chen, Naifu;You, Jun
    • Journal of Power Electronics
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    • v.15 no.3
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    • pp.610-620
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    • 2015
  • An inherent zero-voltage and zero-current-switching phase-shifted full-bridge converter with reverse-blocking insulated-gate bipolar transistor (IGBT) or non-punch-through IGBT is proposed in this paper. This converter not only ensures that the switches in the lagging leg works at zero-current switching, but also minimizes circulating conduction loss without any additional auxiliary circuits. A 1.2 kW hardware prototype is designed, fabricated, and tested to verify the proposed topology. The control loop design procedures with small-signal models are also presented. A simple, low-cost, and robust democratic current-sharing circuit is also introduced and verified in this study. The proposed converter is a suitable alternative for compact, cost-effective applications with high-voltage input.

An Efficient Hardware Implementation of ARIA Block Cipher Algorithm (블록암호 알고리듬 ARIA의 효율적인 하드웨어 구현)

  • Kim, Dong-Hyeon;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.91-94
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    • 2012
  • This paper describes an efficient implementation of ARIA crypto algorithm which is a KS (Korea Standards) block cipher algorithm. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit specified in the standard. To reduce hardware complexity, a hardware sharing is employed, which shares round function in encryption/decryption module with key initialization module. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 33,218 gates and the estimated throughput is about 640 Mbps at 100 MHz.

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