• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.241-241
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• 2008

Macrofore formation in silicon and other semiconductors using electrochemical etching processes has been, in the last years, a subject of great attention of both theory and practice. Its first reason of concern is new areas of macropore silicone applications arising from microelectromechanical systems processing (MEMS), membrane techniques, solar cells, sensors, photonic crystals, and new technologies like a silicon-on-nothing (SON) technology. Its formation mechanism with a rich variety of controllable microstructures and their many potential applications have been studied extensively recently. Porous silicon is formed by anodic etching of crystalline silicon in hydrofluoric acid. During the etching process holes are required to enable the dissolution of the silicon anode. For p-type silicon, holes are the majority charge carriers, therefore porous silicon can be formed under the action of a positive bias on the silicon anode. For n-type silicon, holes to dissolve silicon is supplied by illuminating n-type silicon with above-band-gap light which allows sufficient generation of holes. To make a desired three-dimensional nano- or micro-structures, pre-structuring the masked surface in KOH solution to form a periodic array of etch pits before electrochemical etching. Due to enhanced electric field, the holes are efficiently collected at the pore tips for etching. The depletion of holes in the space charge region prevents silicon dissolution at the sidewalls, enabling anisotropic etching for the trenches. This is correct theoretical explanation for n-type Si etching. However, there are a few experimental repors in p-type silicon, while a number of theoretical models have been worked out to explain experimental dependence observed. To perform ordered macrofore formaion for p-type silicon, various kinds of mask patterns to make initial KOH etch pits were used. In order to understand the roles played by the kinds of etching solution in the formation of pillar arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, N-dimethylformamide (DMF), iso-propanol, and mixtures of HF with water on the macrofore structure formation on monocrystalline p-type silicon with a resistivity varying between 10 ~ 0.01 $\Omega$ cm. The etching solution including the iso-propanol produced a best three dimensional pillar structures. The experimental results are discussed on the base of Lehmann's comprehensive model based on SCR width.

• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.182-187
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• 2005

A large area micro mirror is an optical element that functions as changing an optical path by reflection in integrated optical system. We fabricated the large area silicon mirror by anisotropic etching using MEMS for implementation of integrated optical pickup. In this work, we report the optimum conditions to better fabricate and design, greatly improve mirror surface quality. To obtain mirror surface of $45^{\circ},\;9.74^{\circ}$ off-axis silicon wafer from (100) plane was used in etching condition of $80^{\circ}C$ with 40wt.% KOH solution. After wet etching, polishing process by MR fluid was applied to mirror surface for reduction of roughness. In the next step, after polymer coating on the polished Si wafer, the Si mirror was fabricated by UV curing using a trapezoid bar-type way structure. Finally, we obtained peak to valley roughness about 50 nm in large area of $mm^2$ and it is applicable to optical pickup using blu-ray wavelength as well as infrared wavelength.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.3
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• pp.176-181
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• 2012

Due to the high etch rate and low fabrication cost, the wet etching of silicon using KOH etchant is widely used in MEMS fabrication area. However, anisotropic etch characteristic obstruct intuitional mask design and compensation structures are required for mask design level. Therefore, the accurate modeling for various types of silicon surface is essential for fabrication of three-dimensional MEMS structure. In this paper, we modeled KOH etch profile for MEMS based energy harvester using fuzzy logic. Modeling results are compared with experimental results and it is applied to design of compensation structure for MEMS based energy harvester. Through Fuzzy inference approaches, developed model showed good agreement with the experimental results with limited etch rate information.

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.19-25
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• 1994

When etching rectangular convex corners of silicon using anisotropic etchants such as KOH, deformation of the edges always occurs due to undercutting. Therefore, it is necessary to correct the mass pattern for compensation. Experiments for the compensation method to prevent this phenomenon were carried out. In the result, the compensation pattern of a regular square is suitable for acceleration sensors considering space. With this consequence, silicon piezoresistive acceleration sensor with compensated square pillar type of mass has been fabricated using SDB wafer.

• Journal of the Korean institute of surface engineering
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• v.50 no.5
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• pp.315-321
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• 2017

Antireflective pyramid arrays can be readily obtained via anisotropic etching in alkaline solution (KOH, NaOH), which is widely used in crystalline-Si (c-Si) solar cells. The periodic inverted pyramid arrays show even lower light reflectivity because of their superior light-trapping characteristics. Since this inverted pyramidal structures are mostly achieved using very complex techniques such as photolithograpy and laser processes requiring extra costs, here, we demonstrate the Cu-nanoparticle assisted chemical etching processes to make the inverted pyramidal arrays without the need of photolithography. We have mainly controlled the concentration of $Cu(NO_3)_2$, HF, $H_2O_2$ and temperature as well as time factors that affecting the reaction. Optimal inverted pyramid structure was obtained through reaction parameters control. The reflectance of inverted pyramid arrays showed < 10% over 400 to 1100 nm wavelength range while showing 15~20% in random pyramid arrays.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.25 no.1
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• pp.62-67
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• 2016

This paper presents a silicon nanostructure array embedded in a polymer film. The silicon nanostructure array was fabricated by using basic microelectromechanical systems (MEMS) processes such as photolithography, reactive ion etching, and anisotropic KOH wet etching. The fabricated silicon nanostructure array was transferred into polymer substrates such as polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), and polycarbonate (PC) through the hot-embossing process. In order to determine the transfer conditions under which the silicon nanostructures do not fracture, hot-embossing experiments were performed at various temperatures, pressures, and pressing times. Transfer was successfully achieved with a pressure of 1 MPa and a temperature higher than the transition temperature for the three types of polymer substrates. The transferred silicon nanostructure array was electrically evaluated through measurements with a semiconductor parameter analyzer (SPA).

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.74.1-74.1
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• 2010

단결정 실리콘 태양전지 공정에서 이방성 습식 식각 용액을 이용하여 기판 표면에 피라미드 구조를 형성하는 것을 텍스쳐링이라고 한다. 실리콘 기판의 표면을 식각하여 요철구조를 만들어줌으로써 셀 내부로 입사되는 광량을 증가시켜 태양전지의 단락 전류 및 효율 향상 효과를 얻을 수 있다. 일반적인 태양전지 공정에서는 요철구조를 형성할 시 따로 마스크를 사용하지 않으며, 태양전지 급 웨이퍼를 절삭손상층 식각 한 후, 강염기성 용액과 알코올의 혼합용액에 담가서 이방성 식각을 실시하여 요철 구조를 형성한다. 본 연구는 기존의 텍스쳐링 공정에서 사용되는 대표적인 용액인 수산화칼륨(potassium hydroxide, KOH)과 알코올의 혼합용액과 사메틸수산화암모늄(Tetramethylammonium Hydroxide, TMAH)과 알코올의 혼합용액에 Triton X-100 계면활성제를 각각 첨가하여 실험을 진행하였다. 식각된 태양전지용 실리콘 기판의 표면은 주사전자현미경(Scanning Electron Microscope)을 통하여 관찰하였고, 분광광도계(UV/VIS/NIR Spectrophotometer)로 반사도 값을 측정하여 기판의 특성을 평가하였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.113-120
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• 1994

Silicon flow sensor that can detect the velocity and direction of air flow was designed and fabricated by integrated circuit process and bulk micromachining technique. The flow sensor consists of three-layered dielectric diaphragm, a heater at the center of the diaphragm, and four thermopiles surrounding the heater at each side of diaphragm as sensing elements. This diaphragm structure contributes to improve the sensitivity of the sensor due to excellent thermal isolation property of dielectric materials and their tiny thickness. The flow sensor has good axial symmetry to sense 2-D air flow with the optimized sensing position in the proposed structure. The sensor is fabricated using CMOS compatible process followed by the anisotropic etching of silicon in KOH and EDP solutions to form I$\mu$ m thick dielectric diaphragm as the last step. TCR(Temperature Coefficient of Resistance) of the heater of the fabricated sensors was measured to calculate the operating temperature of the heater and the output voltage of the sensor with respect to flow velocity was also measured. The TCR of the polysilicon heater resistor is 697ppm/K, and the operating temperature of the heater is 331$^{\circ}C$ when the applied voltage is 5V. Measured sensitivity of the sensor is 18.7mV/(m/s)$^{1/2}$ for the flow velocity of smaller than 10m/s.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.9 s.186
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• pp.174-178
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• 2006

Pyramid shape of micro pattern is applied to the light guide panel (LGP) to enhance the uniformity of the brightness of the LCD. The micro pyramids are molded in intaglio on the surface of the LGP. The size of each pyramid is 5$\mu$m $\times$ 5$\mu$m on bottom and the height is about 3.5$\mu$m. The pyramids are distributed on the LGP surface randomly to be sparser where the light comes in and denser at the opposite side as a result of a simulation using lightools$^{TM}$ Based on this design, a silicon pattern master and a nickel stamper are fabricated by MEMS process and electro plating process. Intaglio micro pyramids are fabricated on the 6' of silicon wafer from the anisotropic etching using KOH and the process time, temperature of the KOH solution, etc are optimized to obtain precise shape of the pattern. A Wi stamper is fabricated from this pattern master by electro plating process and the embossed pyramid patterns turns out to be well defined on the stamper. Adopting this stamper to the mold base with two cavities, 1.8' and 3.6' LGPs are injection molded.

• Journal of Sensor Science and Technology
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• v.14 no.1
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• pp.22-27
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• 2005

A thermoelectric flow sensor for small quantity of gas flow rate was fabricated using silicon wafer semiconductor process and bulk micromachining technology. Evanohm R alloy heater and chromel-constantan thermocouples were used as a generation heat unit and sensing parts, respectively. The heater and thermocouples are thermally isolated on the $Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$ laminated membrane. The characteristics of this sensor were observed in the flow rate range from 0.2 slm to 1.0 slm and the heater power from 0.72 mW to 5.63 mW. The results showed that the sensitivities $(({\partial}({\Delta}V)/{\partial}(\dot{q}));{\;}{\Delta}V$ : voltage difference, $\dot{q}$ : flow rate) were increased in accordance with heater power rise and decreasing of flow rate.