• Title/Summary/Keyword: K-mismatch

Search Result 896, Processing Time 0.035 seconds

Separating VNF and Network Control for Hardware-Acceleration of SDN/NFV Architecture

  • Duan, Tong;Lan, Julong;Hu, Yuxiang;Sun, Penghao
    • ETRI Journal
    • /
    • v.39 no.4
    • /
    • pp.525-534
    • /
    • 2017
  • A hardware-acceleration architecture that separates virtual network functions (VNFs) and network control (called HSN) is proposed to solve the mismatch between the simple flow steering requirements and strong packet processing abilities of software-defined networking (SDN) forwarding elements (FEs) in SDN/network function virtualization (NFV) architecture, while improving the efficiency of NFV infrastructure and the performance of network-intensive functions. HSN makes full use of FEs and accelerates VNFs through two mechanisms: (1) separation of traffic steering and packet processing in the FEs; (2) separation of SDN and NFV control in the FEs. Our HSN prototype, built on NetFPGA-10G, demonstrates that the processing performance can be greatly improved with only a small modification of the traditional SDN/NFV architecture.

High Performance CMOS Charge Pumps for Phase-locked Loop

  • Rahman, Labonnah Farzana;Ariffin, NurHazliza Bt;Reaz, Mamun Bin Ibne;Marufuzzaman, Mohammad
    • Transactions on Electrical and Electronic Materials
    • /
    • v.16 no.5
    • /
    • pp.241-249
    • /
    • 2015
  • Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.

Genetic Algorithm for Identification of Time Delay Systems from Step Responses

  • Shin, Gang-Wook;Song, Young-Joo;Lee, Tae-Bong;Choi, Hong-Kyoo
    • International Journal of Control, Automation, and Systems
    • /
    • v.5 no.1
    • /
    • pp.79-85
    • /
    • 2007
  • In this paper, a real-coded genetic algorithm is proposed for identification of time delay systems from step responses. FOPDT(First-Order Plus Dead-Time) and SOPDT(Second-Order Plus Dead-Time) systems, which are the most useful processes in this field, but are difficult for system identification because of a long dead-time problem and a model mismatch problem. Genetic algorithms have been successfully applied to a variety of complex optimization problems where other techniques have often failed. Thus, the modified crossover operator of a real-code genetic algorithm is proposed to effectively search the system parameters. The proposed method, using a real-coding genetic algorithm, shows better performance characteristics when compared to the usual area-based identification method and the directed identification method that uses step responses.

A Digital Current Differential Transformer Protecion Algorithm Minimizing the Effect of DC-offset (DC-offset 영향을 최소화한 변압기보호 디지털 비율차동 계전알고리즘 구현)

  • Kwon, Young-Jin;Kang, Sang-Hee;Lee, Seeng-Jae;Jung, Sung-Kyo
    • Proceedings of the KIEE Conference
    • /
    • 2001.05a
    • /
    • pp.38-41
    • /
    • 2001
  • This paper presents a digital current differential protection algorithm for a transformer in power system. This algorithm uses an FIR filter to improve the performance of the relay. This paper presents a practical method setting the operating slope of the relay and reduce ct mismatch. A series of EMTP simulation results have shown effectiveness of the algorithm under various type of transformers and conditions.

  • PDF

Performance of capacitorless 1T-DRAM cell on silicon-germanium-on-insulator (SGOI) substrate (SGOI 기판을 이용한 1T-DRAM에 관한 연구)

  • Jung, Seung-Min;Oh, Jun-Seok;Kim, Min-Soo;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2010.06a
    • /
    • pp.346-346
    • /
    • 2010
  • A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

  • PDF

Multichannel Blind Equalization using Multistep Prediction and Adaptive Implementation

  • Ahn, Kyung-Seung;Hwang, Ho-Sun;Hwang, Tae-Jin;Baik, Heung-Ki
    • Proceedings of the IEEK Conference
    • /
    • 2001.06a
    • /
    • pp.69-72
    • /
    • 2001
  • Blind equalization of transmission channel is important in communication areas and signal processing applications because it does not need training sequence, nor does it require a priori channel information. Recently, Tong et al. proposed solutions for this problem exploit the diversity induced by antenna array or time oversampling, leading to the second order statistics techniques, fur example, subspace method, prediction error method, and so on. The linear prediction error method is perhaps the most attractive in practice due to the insensitive to blind equalizer length mismatch as well as for its simple adaptive filter implementation. Unfortunately, the previous one-step prediction error method is known to be limited in arbitrary delay. In this paper, we induce the optimal delay, and propose the adaptive blind equalizer with multi-step linear prediction using RLS-type algorithm. Simulation results are presented to demonstrate the proposed algorithm and to compare it with existing algorithms.

  • PDF

Study on Residual Stress in Viscoelastic Thin Film Using Curvature Measurement Method

  • Im, Young-Tae;Park, Seung-Tae;Park, Tae-Sang;Kim, Jae-Hyun
    • Journal of Mechanical Science and Technology
    • /
    • v.18 no.1
    • /
    • pp.12-19
    • /
    • 2004
  • Using LSM (laser scanning method) , the radius of curvature due to thermal deformation in polyimide film coated on Si substrate is measured. Since the polyimide film shows viscoelastic behavior, i.e., the modulus and deformation of the film vary with time and temperature, we estimate the relaxation modulus and the residual stresses of the polyimide film by measuring the radius of curvature and subsequently by performing viscoelastic analysis. The residual stresses relax by an amount of 10% at 100$^{\circ}C$ and 20% at 150$^{\circ}C$ for two hours.

Electronic Structures of Graphene on Ru(0001) : Scanning Tunneling Spectroscopy Study

  • Jang, Won-Jun;Jeon, Jeung-Hum;Yoon, Jong-Keon;Kahng, Se-Jong
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2011.02a
    • /
    • pp.307-307
    • /
    • 2011
  • Graphene is the hottest topic in condensed-matter physics due to its unusual electronic structures such as Dirac cones and massless linear dispersions. Graphene can be epitaxially grown on various metal surfaces with chemical vapor deposition processes. Such epitaxial graphene shows modified electronic structures caused by substrates. Here, local geometric and electronic structures of graphene grown on Ru(0001) will be presented. Scanning tunneling microscopy (STM) and spectroscopy (STS) was used to reveal energy dependent atomic level topography and position-dependent differential conductance spectra. Both topography and spectra show variations from three different locations in rippled structures caused by lattice mismatch between graphene and substrate. Based on the observed results, structural models for graphene on Ru(0001) system were considered.

  • PDF

Thermal Properties of Graphene

  • Yoon, Du-Hee;Lee, Jae-Ung;Son, Young-Woo;Cheong, Hyeon-Sik
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2011.02a
    • /
    • pp.14-14
    • /
    • 2011
  • Graphene is known to possess excellent thermal properties, including high thermal conductivity, that make it a prime candidate material for heat management in ultra large scale integrated circuits. For device applications, the key parameters are the thermal expansion coefficient and the thermal conductivity. There has been no reliable experimental determination on the thermal expansion coefficient of graphene whereas the estimates of the thermal conductivity vary widely. In this work, we estimate the thermal expansion coefficient of graphene on silicon dioxide by measuring the temperature dependence of the Raman spectrum. The shift of the Raman peaks due to heating or cooling results from both the intrinsic temperature dependence of the Raman spectrum of graphene and the strain on the graphene film due to the thermal expansion mismatch with silicon dioxide. By carefully comparing the experimental data against theoretical calculations, it is possible to determine the thermal expansion coefficient. The thermal conductivity is measured by estimating the thermal profile of a graphene film suspended over a circular hole of the substrate.

  • PDF

Characteristics of fluoride/glass as a seed layer for microcrystalline silicon film growth

  • Choi, Seok-Won;Kim, Do-Young;Ahn, Byeong-Jae;Yi, Jun-Sin
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2000.01a
    • /
    • pp.65-66
    • /
    • 2000
  • Various fluoride films on a glass substrate were prepared and characterized to provide a seed layer for crystalline Si film growth. The XRD analysis on $CaF_2/glass$ illustrated (220) preferential orientation and showed lattice mismatch less than 5 % with Si. We achieved a fluoride film with breakdown electric field of 1.27 MV/cm, leakage current density about $10^{-6}$ $A/cm^2$, and relative dielectric constant less than 5.6. This paper demonstrates microcrystalline silicon $({\mu}c-Si)$ film growth by using a $CaF_2/glass$ substrate. The ${\mu}c-Si$ films exhibited crystallization in (111) and (220) planes, grain size of $700\;{\AA}$, crystalline volume fraction over 65 %, dark- and photo-conductivity ratio of 124, activation energy of 0.49 eV, and dark conductivity less than $4{\times}10^{-7}$ S/cm.

  • PDF