• Journal of the Korean Solar Energy Society
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• v.30 no.6
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• pp.102-107
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• 2010

a-Si solar cell has relatively dominant drift current when compared with crystalline solar cell due to the high internal electric field. Such drift current make an impact on the PV module in the local shading. In this paper, the a-Si PV module output characteristics of shading effects was approached in terms of process condition, because of the different deposition layer of thin film lead to rising the resistance. We suggested design condition to ensure the long-term durability of the module with regard to the degradation factors such as hot spot by analyzing the module specification. The result shows a remarkable difference on module uniformity for each shading position. In addition, the unbalanced power loss due to power mismatch of each module could intensify the degradation.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.89-89
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• 2004

• Journal of Power Electronics
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• v.10 no.5
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• pp.485-490
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• 2010

Sensorless control methods are generally used in motor control for home-appliances because of the material cost and manufactureing standard restrictions. The current model-based control algorithm is mainly used for PMSM sensorless control in the home-appliance industry. In this control method, the rotor position is estimated by using the d-axis and q-axis current errors between the real system and a motor model of the position estimator. As a result, the accuracy of the motor model parameters are critical in this control method. A mismatch of the PMSM parameters affects the speed and torque in low speed, steadystate responses. Rotor position errors are mainly caused by a mismatch of the stator resistance. In this paper, a stator resistance compensation algorithm is proposed to improve sensorless control performance. This algorithm is easy to implement and does not require a modification of the motor model or any special interruptions of the controller. The effectiveness of the proposed algorithm is verified through experimental results.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1999.06a
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• pp.305-320
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• 1999

It was grown Er2O3 doped LiNbO3 single crystal thin films with high crystal quality by liquid phase epitaxial (LPE) method. Er2O3 was doped with a concentration of 1, 3, and 5 mol% respectively. After the growth of single crystal thin film, we examined the crystallinity and the lattice mismatch along the c-axis between the film and the substrate with the variation of Er2O3 dopant using X-ray double crystal technique. There were no lattice mismatches along the c-axis for the undoped and the films doped with 1 and 3 mol% of Er2O3. For 5 mol% of Er2O3 doped film, there was a lattice mismatch of 7.86x10-4nm along the c-axis.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.854-859
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• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1327-1337
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• 2017

Photovoltaic (PV) systems are influenced by disproportionate impacts on energy production caused by frequent mismatch cases. The occurrence of multiple maximum power points (MPPs) adds complexity to the tracking process in various PV systems. However, current maximum-power point tracking (MPPT) techniques exhibit limited performance. This paper introduces an enhanced simulated annealing (ESA)-based GMPPT technique against multiple MPP issues in P-V curve with different PV system structures. The proposed technique not only distinguishes global and local MPPs but also performs rapid convergence speed and high tracking accuracy of irradiance changing and restart capability detection. Moreover, the proposed global maximum power tracking algorithm can be applied in the central converter of DMPPT and hybrid PV system to meet various application scenarios. Its effectiveness is verified by simulation and test results.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.535-538
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• 2001

In this paper, we present a novel method to solve the inevitable RGB beam mismatch problem in projection TV receivers. Conventional methods solve the mismatch problem by directly controlling the cathode ray tube (CRT) using the convergence yoke (CY). Unlike conventional methods, the proposed method is based on digital video processing using image warping techniques. Firstly RGB beam projection paths are mathematically modeled. Then based on the modeling, the input video signal to CRT is prewarped so that RGB beams are landed at the same point on the screen. Since the proposed method is based on a digital video processing instead of using CY, it can outperform the conventional method in terms of quality and cost. The experimental results with a real 60´projection TV demonstrate that the proposed method indeed produces converged images on the projection TV screen.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.1
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• pp.168-172
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• 2013

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.12
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• pp.5643-5656
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• 2016

The detection accuracy of steganalysis depends on many factors, including the embedding algorithm, the payload size, the steganalysis feature space and the properties of the cover source. In practice, the cover source mismatch (CSM) problem has been recognized as the single most important factor negatively affecting the performance. To address this problem, we propose a new framework for blind, universal steganalysis which uses traditional steganalyst features. Firstly, cover images with the same statistical properties are searched from a reference image database as aided samples. The test image and its aided samples form a whole test set. Then, by assuming that most of the aided samples are innocent, we conduct outlier detection on the test set to judge the test image as cover or stego. In this way, the framework has removed the need for training. Hence, it does not suffer from cover source mismatch. Because it performs anomaly detection rather than classification, this method is totally unsupervised. The results in our study show that this framework works superior than one-class support vector machine and the outlier detector without considering the image retrieval process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.