• Title/Summary/Keyword: Junction device

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In-vivo Evaluation of Pneumatic Ventricular Assist Device and Durability Improvement (공압식 심실보조장치의 in-vivo 평가 및 내구성 개선)

  • 이상훈;이광호;박성식;서필원;김삼현;강봉진
    • Journal of Biomedical Engineering Research
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    • v.25 no.1
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    • pp.65-70
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    • 2004
  • In this paper, we described 23 cases of animal experiment with our pneumatic ventricular assist device and new durability-improvement method. The blood pump consists of blood housing, and back plate made by the injection molding of isoplast, and the diaphragm fabricated by dipping of polyurethane solution onto the aluminum mold. Its volume was 75 $m\ell$ and in-vitro test showed that maximum output was 4.5 $\ell$/min at the 100 mmHg. The adult female sheep with weight of 50 + 10 kg were employed for tile in-vivo experiments and the mean blood flow was sustained at 3.0 1/min. 4 animals survived more than 15 days and the longest survival time was 28 days. In the prior 10 cases, the major causes of death were the tearing of diaphragm at the diaphragm to blood housing junction. By the new mesh and alumina ball milling methods, the durability was enhanced, and its qualitative and quantitative improvement was proved via the in-vivo and in-vitro methods. Animal experiments demonstrated that all the physiologic parameters a ere maintained within the permissible ranges and no thrombus formation was observed through the visual and blood test. The in-vivo experiments demonstrated our pneumatic ventricular assist device to he one month's bridge to transplantation device.

Variations of the hole injection efficiency with IGBT's collector structure (IGBT의 콜렉터 구조에 따른 홀 주입효율의 변화)

  • Choi, Byung-Sung;Chung, Sang-Koo
    • Proceedings of the KIEE Conference
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    • 1999.07d
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    • pp.1956-1958
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    • 1999
  • The analysis of hole injection efficiency at the p+/n-drift layer junction in non-punchthrough IGBT structure is presented. This analysis takes into account carrier concentration variations by conductivity modulation. Good agreement between this analysis and simulation is found over a wide range of carrier lifetime and current density. The proposed analytical model of the hole injection efficiency as a function of collector width, collector concentration has been verified by device simulator, ATLAS.

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A Study on the Breakdown Characteristics of High Voltage Device using Field Limiting Ring and Side Glass Insulator Wall (전계제한테와 측면 유리 절연층을 사용한 고내압 소자의 항복 특성 연구)

  • Huh, Chang-Su;Chu, Eun-Sang
    • Proceedings of the KIEE Conference
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    • 1995.07c
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    • pp.1072-1074
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    • 1995
  • Zinc-Borosilicate is used as a side insulastor wall to make high breakdown voltage with one Field Limiting Ring in a p-n junction. It is known that surface charge can be yield at the interface of Zinc-Borosilicate Glass/Silicon system. When the glass is used as a side insulator wall, surface charge varied potential distribution and breakdown voltage improved more than 660V without using more FLR.

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The Development of Hot Carrier Immunity Device in NMOSFET's (NMOSFET에서 핫-캐리어 내성의 소자 개발)

  • ;;;;Fadul Ahmed Mohammed
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.365-368
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    • 2002
  • WSW(Wrap Side Wall) is proposed to decrease junction electric field in this paper. WSW process is fabricated after first gate etch, followed NMI ion implantation and deposition & etch nitride layer New WSW structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of WSW and conventional. Also, we design a test pattern including pulse generator, level shifter and frequency divider, so that we can evaluate AC hot carrier degradation on-chip.

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Fabrication of planar type GaInAs PIN photodiode and its characteristics (평면형 GaInAs/InP PIN Photodiode 제작 및 특성)

  • 박찬용
    • Proceedings of the Optical Society of Korea Conference
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    • 1991.06a
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    • pp.135-138
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    • 1991
  • A planar type PIN photodiode has been fabricated and discussed. We used OMVPE systems to grow the structure of u-InP/u-InP/n-InP. P-n junction was formed by Zn-diffusion method at 50$0^{\circ}C$, for 5 minitues. The device characteristics at 5V were as follows: Dark currents were distributed around 1nA. Capacitance was 1.6pF and responsivity was above 0.85 mA/mW for 1.3${\mu}{\textrm}{m}$ wavelength. Measured cut-off frequency(-3dB) at -5V was 1.1㎓.

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A Study on the Experimental Fabrication and Analysis of MOS Photovoltaic Solar Energy Conversion Device (MOS 광전변화소자의 식적에 관한 연구)

  • Ko, Gi-Man;Park, Sung-Hui;Sung, Man-Young
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.33 no.6
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    • pp.203-211
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    • 1984
  • MOS silicon solar cells have been developed using the fixed (interface) charge inherent to thermally oxidized silicon to induce an n-type inversion layer in 1-10 ohm-cm p-type silicon. Higher collection efficiencies are predicted than for diffused junction cells. Without special precautions a conversion efficiency of 14.2% is obtained. A MOS silicon solar cell is described in which an inversion layer forms the active area which is then contacted by means of a MOS grid. The highest efficiency is obtained when the resistivity of the substrate is high.

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A Study on the PN Junction Breakdown Characteristics with Design and Process Parameters of FLR in Power Device Design (전력 반도체 소자의 설계에 있어서 FLR의 Design 및 Process Parameter에 따른 PN접합의 항복특성에 관한 고찰)

  • Song, Dae-Sik;Kang, Ey-Goo;Hwang, Sang-Joon;Sung, Man-Young;Lee, Cheol-Jin
    • Proceedings of the KIEE Conference
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    • 1995.07c
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    • pp.1146-1148
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    • 1995
  • To improve the breakdown characteristics of vertical power devices, field limiting ring(FLR) is popularly used. In this paper, at vertical power device having $300{\sim}600V$ breakdown voltage, FLR thecnique is considered, by two dimensional computer simulator, with the various of parameters; number of FLR, seperation distance of first FLR from the main juncton and second FLR from the first FLR, doping concentration and thickness of epi-layer, etc.. Below $40{\mu}m$ epi thickness, and for the case of one FLR, the maximum breakdown voltage, 580V is obtained.

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Design of high speed-low voltage LVDS driver circuit with the novel ESD protection device (새로운 구조의 ESD 보호소자를 내장한 고속-저전압 LVDS Driver 설계)

  • Lee, Jae-Hyun;Kim, Kui-Dong;Kwon, Jong-Ki;Koo, Yong-Seo
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.731-734
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    • 2005
  • In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.

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Nanoscale NiO for transparent solid state devices

  • Patel, Malkeshkumar;Kim, Joondong;Park, Hyeong-Ho
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.243.2-243.2
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    • 2015
  • We report a high-performing nanoscale NiO thin film grown by thermal oxidation of sputtered Ni film. The structural, physical, optical and electrical properties of nanoscale NiO were comprehensively investigated. A quality transparent heterojunction (NiO/ZnO) was formed by large-area applicable sputtering deposition method that has an extremely low saturation current of 0.1 nA. Considerable large rectification ratio of more than 1000 was obtained for transparent heterojunction device. Mott-Schottky analyses were applied to develop the interface of NiO and ZnO by establishing energy diagrams. Nanoscale NiO has the accepter carrier concentration of the order of 1018 cm-3. Nanoscale NiO Schottky junction device properties were comprehensively studied using room temperature impedance spectroscopy.

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