• Proceedings of the KSME Conference
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• 2008.11b
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• pp.2658-2663
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• 2008

In the present study, we designed a microfluidic flatform that generates monodisperse droplets with diameters ranging from hundreds of nanometers to several micrometers. To generate fine droplets, T-junction and flow-focusing geometry are integrated into the microfluidic channel. Relatively large aqueous droplets are generated at the upstream T-junction and transported toward the flow-focusing geometry, where each droplet is broken up into the targeted size by the action of viscous stresses. Because the droplet prior to rupture blocks the straight channel that leads to the flow-focusing geometry, it moves very slowly by the pressure difference applied between the advancing and receding regions of the moving droplet. This configuration enables very low flow rate of inner fluid and higher flow rate ratio between inner and outer fluids at the flow-focusing region. It is shown that the present microfluidic device can generate droplets with diameters about 1 micrometer size and standard deviation less than 3%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.453-456
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• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.

• Progress in Superconductivity
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• v.3 no.1
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• pp.41-44
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• 2001

We report the current transport properties of a normal metal/organic conductor/ superconductor tunnel junction as a novel high- $T_{c}$ superconducting three terminal device. The organic copper (II) phthalocyanine (Cu-Pc) layer was used far a polaronic quasiparticle (QP) injector. The injection of polaronic QP from the Cu-Pc interlayer into a superconductor $Bi_2$$Sr_2$$CaCu_2$ $O_{8+}$ $\delta$/(BSCCO) thin film generated a substantially larger nonequilibrium effect as compared to the normal QP injection current. The tunneling spectroscopy of an Au/cu-PC/BSCCO junction exhibited a zero bias conductance peak which may be due to Andreev reflection at a Cu-Pc/d-wave superconductor junction.n..

• Applied Chemistry for Engineering
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• v.9 no.5
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• pp.710-714
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• 1998

Organic electroluminescence devices (ELD) with hetero-junction structure were fabricated utilizing poly(p-phenylne vinylene) (PPV) as emitting layer and electron transport layer (ETL). 2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (PBD) was used as an electron transport agent. Copolymers with stilbene type comonomers, such as poly(styrene-co-PVTS), poly(styrene-co-MeO-PVTS) and poly(styrene-co-MeO-ST) were synthesized to be used as a matrix polymer to disperse electron transport agent (PBD). Among the hetero-junction EL devices fabricated with the above materials, the device with poly(styrene-co-PVTS) as matrix polymer for ETL gave the highest luminance ($120.7cd/m^2$, 13 V). EL devices made with poly(styrene-co-MeO-PVTS) or poly(styrene-co-MeO-ST) matrix exhibited lower luminance than the one with polystyrene matrix and the single layer EL (ITO/PPV/Mg) device.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.1-8
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• 2003

In this study, the high performance BCD device structure which satisfies the high voltage and fast switching speed characteristics is devised. Through the process and device simulation, optimal process spec. & device spec. are designed. We adapt double buried layer structure, trench isolation process, n-/p-drift region formation and shallow junction technology to optimize an electrical property as mentioned above. This I.C consists of 20V level high voltage bipolar npn/pnp device, 60V level LDMOS device, a few Ampere level VDMOS, 20V level CMOS device and 5V level logic CMOS.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.6
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• pp.37-43
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• 2017

This review investigates the basic principle of physical interactions and failure mechanisms introduced in the materials and inner parts of semiconducting components under electromagnetic pulses (EMPs). The transfer process of EMPs at the semiconducting component level can be explained based on three layer structures (air, dielectric, and conductor layers). The theoretically absorbed energy can be predicted by the complex reflection coefficient. The main failure mechanisms of semiconductor components are also described based on the Joule heating energy generated by the coupling between materials and the applied EMPs. Breakdown of the P-N junction, burnout of the circuit pattern in the semiconductor chip, and damage to connecting wires between the lead frame and semiconducting chips can result from dielectric heating and eddy current loss due to electric and magnetic fields. To summarize, the EMPs transferred to the semiconductor components interact with the chip material in a semiconductor, and dipolar polarization and ionic conduction happen at the same time. Destruction of the P-N junction can result from excessive reverse voltage. Further EMP research at the semiconducting component level is needed to improve the reliability and susceptibility of electric and electronic systems.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• Journal of Information Display
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• v.8 no.2
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• pp.20-24
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• 2007

Efficient white organic light-emitting diodes are fabricated with the blue and red electroluminescent (EL) units electrically connected in a stacked tandem structure by using a transparent doped organic p/n junction. The blue and red EL units consist of the light-emitting layer of 1,4-bis(2,2-diphenyl vinyl)benzene (DPVBi) and 4-dicyanomethylene-2-methyl-6-[2-(2,3,6,7-tetrahydro-1H,5H-benzo[i,j] quinolizin-8-yl)vinyl]-4H-pyran) (DCM2) doped tris(8-hydroxyquinoline) aluminum $(Alq_3)$, respectively. The organic p-n junction consists of ${\alpha}-NPD$ doped with $FeCl_3$ (15 % by weight ratio) and $Alq_3$ doped with Li (10 %). The EL spectra exhibit two peaks at 448 and 606 nm, resulting in white light-emission with the Commission Internationale d'Eclairage (CIE) chromaticity coordinates of (0.36, 0.24). The tandem device shows the quantum efficiency of about 2.2 % at a luminance of 100 $cd/m^2$, higher than individual blue and red EL devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.3
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.