• 한국자기학회:학술대회 개요집
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• 한국자기학회 2007년도 The 1st International Symposium on Advanced Magnetic Materials
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• pp.24.2-24.2
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• 2007

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2007년도 The 1st International Symposium on Advanced Magnetic Materials
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• pp.132.2-132.2
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• 2007

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.181-184
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• 1999

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

• 한국결정학회지
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• 제12권3호
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• pp.162-165
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• 2001

The EDL (Embedded DRAM and Logic) technologies with stack cell capacitors based on NO dielectric and Co-silicided source/drain junctions using a Ti capping material, were successfully implemented. The employed Co-silicided film exhibited junction leakage characteristics comparable to those of non-silicided junctions. Improved device characteristics without degradation of I/sub off/ was also achieved.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2005년도 동계학술연구발표회 및 2차 아시안포럼
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• pp.106-106
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• 2005

• Transactions on Electrical and Electronic Materials
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• 제18권2호
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• pp.70-73
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• 2017

We investigated n-i-p type single junction hydrogenated amorphous silicon oxide solar cells. These cells were without front surface texture or back reflector. Maximum power point efficiency of these cells showed that an optimized device structure is needed to get the best device output. This depends on the thickness and defect density ($N_d$) of the active layer. A typical 10% photovoltaic device conversion efficiency was obtained with a $N_d=8.86{\times}10^{15}cm^{-3}$ defect density and 630 nm active layer thickness. Our investigation suggests a correlation between defect density and active layer thickness to device efficiency. We found that amorphous silicon solar cell efficiency can be improved to well above 10%.

• E2M - 전기 전자와 첨단 소재
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• 제8권6호
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• pp.708-714
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• 1995

We have discussed the buried-channel(BC) behavior through the subthreshold characteristics of submicron PMOSFET device fabricated with twin well CMOS process. In this paper, we have guessed the initial conditions of ion implantation using process simulation, obtained the subthreshold characteristics as a function of process parameter variation such as threshold adjusting ion implant dose($D_c$), channel length(L), gate oxide thickness($T_ox$) and junction depth of source/drain($X_j$) using device simulation. The buried channel behavior with these process prarameter variation were showed apparent difference. Also, the fabricated pMOSFET device having different channel length represented good S.S value and low leakage current with increasing drain voltage.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2008년도 Asian Magnetics Conference
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• pp.188.1-188.1
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• 2008

• Progress in Superconductivity
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• 제4권2호
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• pp.99-103
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• 2003

We studied the nonequilibrium superconductivity due to tunnel injection of polaronic quasiparticle (QP) from organic photoconductor. The transport properties of an organic copper (II) phthalocyanine (Cu -Pc)/d-wave superconductor were investigated in dark and under ultraviolet (UV) radiation for performance of a novel $high -T_{c}$ superconducting three terminal device. We observed that the injection of polaronic QP from the organic Cu -Pc film into the $Bi_2$S $r_2$$CaCuO_{8+{\delta}}$ film generated a substantially larger nonequilibrium effect as compared to the normal QP injection current. We could increase the current gain by UV excitation of the organic photoconductor injector. The tunneling spectroscopy of a Cu -Pc/BSCCO junction exhibited a small enhancement of the zero bias conductance peak under the W excitation. The above phenomena are of importance in developing optically controlled three terminal superconducting device.e.

• 대한전기학회논문지
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• 제45권4호
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• pp.562-567
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• 1996

A new lateral MOS controlled thyristor, named Shorted Anode LMCT(SA-LMCT), is proposed and analyzed by a two-dimensional device simulation. The device structure employs the implanted n+ layer which shorts the p+ anode together by a common metal electrode and provides a electron conduction path during turn-off period. The turn-off is achieved by not only diverting the hole current through the p+ cathode short but also providing the electron conduction path from the n-base into the n+ anode electrode. In addition, the modified shorted anode LMCT, which has an n+ short junction located inside the p+ anode junction, is also presented. It is shown that the modified SA-LMCT enjoys the advantage of no snap-back behavior in the forward characteristics with little sacrificing of the forward voltage drop. The simulation result shows that the turn-off times of SA-LMCT can be reduced by one-forth and the maximum controllable current density may be increased by 45 times at the expense of 0.34 V forward voltage drop as compared with conventional LMCT. (author). 11 refs., 6 figs., 1 tab.