• ETRI Journal
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• v.42 no.2
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• pp.258-271
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• 2020

A correlation exists between luminance samples and chrominance samples of a color image. It is beneficial to exploit such interchannel redundancy for color image compression. We propose an algorithm that predicts chrominance components Cb and Cr from the luminance component Y. The prediction model is trained by supervised learning with Laplacian-regularized least squares to minimize the total prediction error. Kernel principal component analysis mapping, which reduces computational complexity, is implemented on the same point set at both the encoder and decoder to ensure that predictions are identical at both the ends without signaling extra location information. In addition, chrominance subsampling and entropy coding for model parameters are adopted to further reduce the bit rate. Finally, luminance information and model parameters are stored for image reconstruction. Experimental results show the performance superiority of the proposed algorithm over its predecessor and JPEG, and even over JPEG-XR. The compensation version with the chrominance difference of the proposed algorithm performs close to and even better than JPEG2000 in some cases.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.493-496
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• 2000

본 논문에서는 TMS320C6201 DSP (Digial Signal Processor)를 이용하여 실시간 영상 부호화기를 구현하였다. 기본적인 영상 압축 방법으로는 baseline-JPEG을 사용하였고 이에 움직임 검출 알고리즘을 부가하여 영상의 시간적인 중복성을 제거하였다. 특히 저속 메모리와 고속 메모리의 효율적인 분배 사용, 계산량이 많은 모듈의 최적화, 데이터의 병렬 연산과 DMA (Direct Memory Access)를 이용한 데이터 전송 등의 방법을 통하여 실시간 영상 부호화기의 고속 영상 처리에 중점을 두었다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.1
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.913-921
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• 2007

Retargetable compiler which generates executable code for a target processor and performance profiler are required to design a processor optimized for a specific application. This paper presents an architecture exploration methodology based on ADL (Architecture Description Language). We synthesized instruction set and optimized processor structure using information extracted from application program. The information of operation sequences executed frequently and register usage are used for processor optimization. Architecture exploration has been performed for JPEG encoder to show the effectiveness of the system. The ASIP designed using the proposed method shows 1.97 times better performance.

• International Journal of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.22-30
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• 2024

Image compression-decompression methods have become increasingly crucial in modern times, facilitating the transfer of high-quality images while minimizing file size and internet traffic. Historically, early image compression relied on rudimentary codecs, aiming to compress and decompress data with minimal loss of image quality. Recently, a novel compression framework leveraging colorization techniques has emerged. These methods, originally developed for infusing grayscale images with color, have found application in image compression, leading to colorization-based coding. Within this framework, the encoder plays a crucial role in automatically extracting representative pixels-referred to as color seeds-and transmitting them to the decoder. The decoder, utilizing colorization methods, reconstructs color information for the remaining pixels based on the transmitted data. In this paper, we propose a novel approach to image compression, wherein we decompose the compression task into grayscale image compression and colorization tasks. Unlike conventional colorization-based coding, our method focuses on the colorization process rather than the extraction of color seeds. Moreover, we employ the Denoising Diffusion Null-Space Model (DDNM) for colorization, ensuring high-quality color restoration and contributing to superior compression rates. Experimental results demonstrate that our method achieves higher-quality decompressed images compared to standard JPEG and JPEG2000 compression schemes, particularly in high compression rate scenarios.

• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.917-923
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• 2011

In this paper, a new prediction based embedded compression (EC) codec algorithm for the JPEG2000 encoder system is proposed to reduce excessive memory requirements. The EC technique can reduce the 50 % memory requirement for intermediate low-frequency coefficients during multiple discrete wavelet transform (DWT) stages compared with direct implementation of the DWT engine of this paper. The LOCO-I predictor and MAP are widely used in many lossless picture compression codec. The proposed EC algorithm use these predictor which are very simple but surprisingly effective. The predictive EC scheme adopts a forward adaptive quantization and fixed length coding to encoding the prediction error. Simulation results show that our LOCO-I and MAP based EC codecs present only PSNR degradation of 0.48 and 0.26 dB in average, respectively. The proposed algorithm improves the average PSNR by 1.39 dB compared to the previous work in [9].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.12
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• pp.2714-2726
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• 1997

In this paper, adaptive symbol changes-based medical image compression method is presented. First, the differenctial image domain is obtained using the differentiation rules or obaptive predictors applied to original mdeical image. Also, the algorithm determines the context associated with the differential image from the domain. Then prediction symbols which are thought tobe the most probable differential image values are maintained at a high value through the adaptive symbol changes procedure based on estimates of the symbols with polarity coincidence between the differential image values to be coded under to context and differential image values in the model template. At the coding step, the differential image values are encoded as "predicted" or "non-predicted" by the binary adaptive arithmetic encoder, where a binary decision tree is employed. The simlation results indicate that the prediction hit ratios of differential image values using the proposed algorithm improve the coding gain by 25% and 23% than arithmetic coder with ISO JPEG lossless predictor and arithmetic coder with differentiation rules or adaptive predictors, respectively. It can be used in compression part of medical PACS because the proposed method allows the encoder be directly applied to the full bit-planes medical image without a decomposition of the full bit-plane into a series of binary bit-planes as well as lower complexity of encoder through using an additions when sub-dividing recursively unit intervals.

• Journal of Broadcast Engineering
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• v.7 no.2
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• pp.192-201
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• 2002

This paper develops a novel robust information hiding technique that uses channel codes derived from the error-correcting coder. The message encoded by the cover encoder is hidden in DCT transform domain of the cover image. The method exploits the sensitivity of human eyes to adaptively embed a visually recognizable message in an image without affecting the perceptual quality of the underlying cover image. Experimental results show that the proposed data hiding technique is robust to cropping operations, lossy JPEG compression, noise interference and secure against known stego attacks. The performance of the proposed scheme with turbo coder is superior to that without turbo coder.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.06a
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• pp.25-29
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• 1997

The present block-based DCT encoder transforms images regardless of layers and then simply partitions the transformed data into a few layers, for example low and high frequency bands in JPEG. Yet, it fails to utilize the similarity of coefficients in each band. Therefore, we combine the subband coder and the block-based DCt coder in this paper. The new coding scheme enables the data to automatically be classified into several layers and increases the efficiency of transform. Various possible coding structures are investigated and the simulation results are also provided.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.