• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.207-213
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• 2006

In this paper, we reduce the computational complexity to find the minimum distance of RA codes by searching only valid codewords using repetition part. Since LDPC codes have repetition part like RA codes, we also apply this algorithm for computing the minimum distance of LDPC codes. The minimum distance dominates the code performance at high signal-to-noise ratios(SNRs) and in turn allows an estimate of the error floor. The proposed algorithm computes the minimum distance without any constraint on code structures. The minimum distances of LDPC codes and RA codes with large interleavers of practical importance are computed and used to obtain the error floor, which is compared with the performance of the iterative decoding.

• ETRI Journal
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• v.25 no.1
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• pp.1-8
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• 2003

This paper introduces an efficient iterative decoding method for high-dimensional block turbo codes. To improve the decoding performance, we modified the soft decision Viterbi decoding algorithm, which is a trellis-based method. The iteration number can be significantly reduced in the soft output decoding process by applying multiple usage of extrinsic reliability information from all available axes and appropriately normalizing them. Our simulation results reveal that the proposed decoding process needs only about 30% of the iterations required to obtain the same performance with the conventional method at a bit error rate range of $10^{-5}\;to\;10^{-6}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.438-443
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• 2008

The efficient method to implement the Max-Log-MAP algorithm is proposed by modifying the conventional algorithm. It is called a parallel soft output Viterbi algorithm (SOVA) and the rigorous proof is given for the equivalence between the Max-Log-MAP algorithm and the parallel SOVA. The parallel SOVA is compared with the conventional algorithms and we show that it is an efficient algorithm implementing the modified SOVA in parallel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.10
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• pp.585-592
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• 2014

It is well known that serial belief propagation (BP) decoding for low-density parity-check (LDPC) codes achieves faster convergence without any increase of decoding complexity per iteration and bit error rate (BER) performance loss than standard parallel BP (PBP) decoding. Serial BP (SBP) decoding, such as horizontal SBP (H-SBP) decoding or vertical SBP (V-SBP) decoding, updates check nodes or variable nodes faster than standard PBP decoding within a single iteration. In this paper, we propose combined horizontal-vertical SBP (CHV-SBP) decoding. By the same reasoning, CHV-SBP decoding updates check nodes or variable nodes faster than SBP decoding within a serialized step in an iteration. CHV-SBP decoding achieves faster convergence than H-SBP or V-SBP decoding. We compare these decoding schemes in details. We also show in simulations that the convergence rate, in iterations, for CHV-SBP decoding is about $\frac{1}{6}$ of that for standard PBP decoding, while the convergence rate for SBP decoding is about $\frac{1}{2}$ of that for standard PBP decoding. In simulations, we use recently proposed generalized LDPC (GLDPC) codes with binary cyclic codes (BCC).

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.759-762
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• 1999

In this paper, we introduce the concept of a HAPS(High Altitude Platform Station) system which is expected to be a next generation communication system and suggest several error correcting codes to provide high quality services. Since a HAPS system encounters serious signal attenuation due to rain and scattering in the air, concatenated codes which have a high coding gain is considered to be a proper error correcting method. In this paper, we provide performance analyses result of two candidate coding schemes for a HAPS. The first one is a conventional concatenated coding scheme, and the second one is a iterative decoding method known as Turbo Codes.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.5
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• pp.738-745
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• 2009

Underwater acoustic communication has multipath error because of reflection by sea-level and sea-bottom. The multipath of underwater channel causes receive signal to make error floor. In this paper, we propose the underwater communication system using various channel coding schemes such as RS coding, convolutional code, turbo code and concatenated code for overcoming the multipath effect in underwater channel. As shown in simulation results, characteristic of multipath error is similar to that of random error. So interleaver has not effect on error correcting. For correcting of error floor by multipath, it is necessary to use strong channel codes like turbo code. Turbo code is one of the iterative codes. And the performance of concatenated codes including RS code has better performance than using singular channel codes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1C
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• pp.1-8
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• 2005

In this paper, we present a novel LDPC code construction called as semi-algebra low density parity check(LDPC) codes which is one kind of deterministic LDPC code based on dual-diagonal sub-matrix. The constructing method results in a class of high rate LDPC codes. Codes in this class have a large girth and good minimum distances. Furthermore, they can be implemented by simple parallel array architecture using cyclic shift register and perform well with the iterative decoding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.139-147
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• 2010

A novel turbo coded modulation scheme, called turbo-APPM, for deep space optical communications is constructed. The constructed turbo-APPM is a serial concatenations of turbo codes, an accumulator and a pulse position modulation (PPM), where turbo codes act as an outer code while the accumulator and the PPM act together as an inner code. The generator polynomial and the puncturing rule for generating turbo codes are chosen to show the low bit error rate. At the receiver, the joint decoding is performed by exchanging soft information iteratively between the inner decoder and the outer decoder. In the outer decoder, a local iterative decoding for turbo codes is conducted before transferring soft information to the inner decoder. Poisson distribution is used to model the deep space optical channel. It is shown by simulations that the constructed turbo-APPM provides coding gains over all previously proposed schemes such as LDPC-APPM, RS-PPM and SCPPM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.191-199
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• 2005

Space-time turbo codes have been studied extensively as a powerful and bandwidth efficient error correction code over the wireless communication environment. In this paper, the efficient algorithm for decoding space-time turbo codes is proposed. The proposed method reduces the computational complexity by approximating a prior information for a iterative decoder. The performance of space-time turbo codes is also analyzed by using the fixed point implementation and the efficient method for approximating the Log-MAP algorithm is proposed. It is shown that the BER performance of the proposed method is close to that of the Log-MAP algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.488-496
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• 2016

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.