1 |
R. G. Gallager, "Low-density parity-check codes," IRE Trans. Inf. Theory, vol. IT-8, pp. 21-28, Jan. 1962.
|
2 |
D. J. C. MacKay, "Good error correcting codes based on very sparse matrices," IEEE Trans. Inf. Theory, vol. 45, no. 2, pp. 399-431, Mar. 1999.
DOI
ScienceOn
|
3 |
T. Richardson, A. Shokrollahi, and R. Urbanke, "Design of capacity-approaching low-density parity-check codes," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 619-637, 2001.
DOI
ScienceOn
|
4 |
T. J. Richardson and R. Urbanke, "The capacity of low-density parity-check codes under message-passing decoding," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 599-618, 2001.
DOI
ScienceOn
|
5 |
J. Pearl, Probabilistic reasoning in intelligent systems: networks of plausible inference, San Mateo, Morgan Kaufmann, CA, 1988.
|
6 |
J. Zhang and M. Fossorier, "Shuffled iterative decoding," IEEE Trans. Commun., vol. 53, pp. 209-213, Feb. 2005.
DOI
ScienceOn
|
7 |
J. Zhang, Y. Wang, and M. Fossorier, "Replica shuffled iterative decoding," in Proc. IEEE Int. Symp. Inf. Theory, pp. 454-458, Adelaide, Australia, Sept. 2005.
|
8 |
X. Liu, J. Cai, and L. Wu, "Improved decoding algorithm of serial belief propagation with a stop updating criterion for LDPC codes and applications in patterned media storage," IEEE Trans. Magnetics, vol. 49, no. 2, pp. 829-836, Feb. 2013.
DOI
|
9 |
Y. Ueng, B. Yang, C. Yang, H. Lee, and J. Yang, "An efficient multi-standard LDPC decoder design using hardware-friendly shuffled decoding," IEEE Trans. Circuits and Systems I, vol. 60, no. 3, pp. 743-756, Mar. 2013.
DOI
|
10 |
D. Hocevar, "A reduced complexity decoder architecture via layered decoding of LDPC codes," in Proc. Signal Processing Systems (SIPS), pp. 107-112, Austin, Texas, USA, Oct. 2004.
|
11 |
M. M. Mansour and N. R. Shanbhag, "High-throughput LDPC decoders," IEEE Trans. Very Large Scale Integration Systems(VLSI), vol. 11, pp. 976-996, 2003.
DOI
|
12 |
Y. Ueng, C. Leong, C. Yang, C. Cheng, K. Liao, and S. Chen, "An efficient layered decoding architecture for nonbinary QC-LDPC codes," IEEE Trans. Circuits and Systems I, vol. 59, no. 2, pp. 385-398, Feb. 2012.
DOI
|
13 |
K. Chung, "Generalised low-density paritycheck codes with binary cyclic codes as component codes," IET commun. vol. 6, no. 12, pp. 1710-1715, 2012.
DOI
|
14 |
M. Lentmaier and K. Zigangirov, "On generalized low-density paritycheck codes based on Hamming component codes," IEEE Commun. Lett., vol. 3, no. 8, pp. 248-250, Aug. 1999.
DOI
|
15 |
I. Djordjevic, L. Xu, T. Wang, and M. Cvijetic, "GLDPC codes with Reed-Muller component codes suitable for optical communications," IEEE Commun. Lett., vol. 12, no. 9, pp. 684-686, Sept. 2008.
DOI
|
16 |
L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal decoding of linear codes for minimizing symbol error rate," IEEE Trans. Inf. Theory, vol. 20, pp. 284-287, 1974.
|
17 |
N. Miladinovic and M. Fossorier, "Generalized LDPC codes with Reed-Solomon and BCH codes as component codes for binary channels," in Proc. IEEE GLOBECOM, p. 6, St. Louis, Missouri, USA, Nov. 2005.
|