• 한국철도학회:학술대회논문집
• /
• 한국철도학회 2011년도 정기총회 및 추계학술대회 논문집
• /
• pp.685-692
• /
• 2011

DC/DC switching power converters produce DC output voltages from different DC input sources. The converters can be used in regenerative braking of DC motors to return energy back in the supply, resulting in energy savings for the systems containing frequent stops. The current mode DC/DC converter is composed of a PWM (pulse width modulation) controller, a MOSFET, and inductor, etc. Pulse width modulation is applied to control and regulate the total output voltage. It is shown that the variation of threshold voltage at MOSFET and the offset voltage increase caused by radiation effects make the PWM pulse unstable. In the PWM operation, the missing pulses, the changes in pulse width, and a change in the period of the output waveform are studied by simulation program with integrated circuit emphasis (SPICE) and experiments.

• 전자공학회논문지A
• /
• 제32A권11호
• /
• pp.79-85
• /
• 1995

In this paper, an epi layer and a device structure for InP/InGaAs p-i-n/HBT OEIC is designed for a receiving frontend of high speed optical communications. A 3 stage transimpedance circuit using the p-i-n/HBT device is also designed by SPICE simulations for a high sensitivity including ISI noises at a given bit rate. Our simulations show that the Personick's assumption which is not commonly satisfied have estimated a photoreceiver sensitivity too high, so thus we have to also consider ISI noises in OCIC receiver designs.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권4호
• /
• pp.397-404
• /
• 2012

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2000년도 전력전자학술대회 논문집
• /
• pp.1-5
• /
• 2000

This paper deals with the modeling and analysis of the high voltage flyback transformer (HVFBT) often utilized in small-sized high voltage DC power supplies. The parasitic capacitance of th HVFBT with the large turns of the secondary winding causes the undesirable parasitic resonance in the transient state which produces the high current stress and limits the switching frequency of the converter. In order to analyze this phenomenon the equivalent circuit model including the parasitic capacitance is derived and the frequency characteristics are provided. The parasitic resonance in the switching states is also investigated based on this equivalent circuit model. The derived model and analysis is finally validated through the SPICE simulation and experiments.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1992년도 하계학술대회 논문집 B
• /
• pp.645-648
• /
• 1992

In a capacitor-discharge impulse magnetizer, one of the magnetic application system, a magnet is magnetized by the discharging current of capacitors. The conventional design of the magnetizer has been based on many year's experience. The behaviour of flux in the magnetizer should be calculated in order to produce the desired magnets. The analysis of the flux distribution is quite difficult. This is because both the magnetizing current and the applied voltage to the magnetizer are unknown. This paper describes the development of computer model for a capacitor-discharge impulse magnetizer using SPICE. Also, the detailed distribution of the flux density in a magnet magnetized by the impulse magnetizer be analyed.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
• /
• pp.1560-1563
• /
• 1987

This paper is concerned with time delay modeling of ED MOS gates which takes into account the slope of input waveform as well as the load condition. Defining the delay time as the time required to charge/discharge the load to the physical reference level, the rise/fall delay times arc derived in an explicit formula in terms of the sum of optimally weighted current unbalances at two end points of voltage transition. The proposed model is computationally effective and the error is typically within 10% of the SPICE results.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1993년도 추계학술대회 논문집
• /
• pp.93-96
• /
• 1993

BiCMOS technology, which combines CMOS and bipolar technology, offers the possibility of achieving both very high density and high performance. In this paper, the characteristics of BiCMOS and CMOS circuits, especilly the delay time is studied. BiCMOS inverter, which has high drive ability because of bipolar transistor, drives high load capacitance and has low-power characteristics because the current flows only during switching transient just like the CMOS gate. BiCMOS inverter has the less dependence on load capacitance than CMOS inverter. SPICE that has been used for electronic circuit analysis is chosen to simulate these circuits and the characteristics is discussed.

• 제어로봇시스템학회논문지
• /
• 제18권4호
• /
• pp.371-374
• /
• 2012

DC/DC switching power converters produce DC output voltages from different stable DC input sources regulated by a bi-polar transistor. The converters can be used in regenerative braking of DC motors to return energy back in the supply, resulting in energy savings for the systems containing frequent stops. The voltage mode DC/DC converter is composed of a PWM (Pulse Width Modulation) controller, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an inductor, and capacitors, etc. PWM is applied to control and regulate the total output voltage. It is shown that the output of DC/DC converter depends on the variation of threshold voltage at MOSFET and the variation of pulse width. In the PWM operation, the missing pulses, the changes in pulse width, and a change in the period of the output waveform are studied by SPICE (Simulation Program with Integrated Circuit Emphasis) and experiments.

• 전자공학회논문지A
• /
• 제33A권5호
• /
• pp.180-187
• /
• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• Journal of electromagnetic engineering and science
• /
• 제15권4호
• /
• pp.258-265
• /
• 2015

A de-embedding method for multiport networks, especially for coupled odd interconnection lines, is presented in this paper. This method does not require a conversion from S-parameters to T-parameters, which is widely used in the de-embedding technique of multiport networks based on cascaded simple two-port relations, whereas here, we apply an operation to the S-matrix to generate all the uncoupled and coupled coefficients. The derivation of the method is based on the relations of incident and reflected waves between the input of the entire network and the input of the intrinsic device under test (DUT). The characteristics of the intrinsic DUT are eventually achieved and expressed as a function of the S-parameters of the whole network, which are easily obtained. The derived coefficients constitute ABCD-parameters for a convenient implementation of the method into cascaded multiport networks. A validation was performed based on a spice-like circuit simulator, and this verified the proposed method for both uncoupled and coupled cases.