• 제목/요약/키워드: Is-Spice

검색결과 478건 처리시간 0.031초

한국의 개고기 음식에 대한 고찰 (Dog Meat Foods in Korea)

  • 안용근
    • 한국식품영양학회지
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    • 제12권4호
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    • pp.397-408
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    • 1999
  • In the year of 1998 the heads of dog raised in Korea were 1,846,411 and the number of the households raising dogs is 819,112 which means that the heads of pet dog and edible dos were 819,112 and 1,027,299, respectively, because each house raised about one pet dog and one edible dog breeder raised hundreds of dog. in 1998 the number of exported dogs came to 28 heads and that of imported dogs was 296 heads. But edible dog that was slaughtered or processed has not been reported to be exported or imported. It is known that at the Shenyang Xingshan Food Ltd in Shenyang, Chinese, 300,000 heads of dogs were rais-ed slaughtered and processed of dog meat per year, and 20% of them were exported. In Korea the cook of dog meat is a special food culture with a long history. During the Chosun dynasty dog meat had been eaten to be cooked diversely such as Gaejangkuk(a soup) Suyuk(a boiled meat) Sundae(a sausage) Kui(a roasted meat) Gaezim(a steamed meat) Nurumi(a meat roasted or fried to which lot of spice paste are added) Gaesoju(an extract) Musulju(a wine) Musuldang(a sweet cane) Now it is cooked as Bosintang(a soup) Suyuk (a boiled meat) Jeongol (boiled meat mixed with spices vegetables and water on the pot) Duruchigi(boiled meat added spice vegatasble and slightly roasted) Muchim(boiled meat added by spice and mixed) Gaesoju(an extract) with the number of recipes lessened compared with those of the old times. The reason is due to the intervention and criticism from foreign countries. But foreigner's blame for the dog meat is absurd and excessive action because Korea raises exceptional dogs which are edible.

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TFT-LCD 특성 분석을 위한 poly-Si TFT 소자 모델링 및 회로 시뮬레이션 (Modeling of Poly-Si TFT and Circuit Simulation for the Analysis of TFT-LCD Characteristics)

  • 손명식;류재일;심성융;장진;유건호
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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    • pp.314-317
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    • 2000
  • In order to analyze the characteristics of complicated TFT-LCD (Thin Film Transistor-Liquid Crystal Display) circuits, it is indispensible to use simulation programs. In this study, we present a systematic method of extracting the input parameters of poly-Si TFT for Spice simulation. This method is applied to two different types of poly-Si TFTs fabricated in our group with good results. Among the Spice simulators, Pspice has the graphic user interface feature making the composition of complicated circuits easier. We added successfully a poly-Si TFT model on the Pspice simulator, which would contribute to efficient simulations of poly-Si TFT-LCD pixels and arrays.

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POWER LIGBT의 모델링에 관한 연구 (A study on Mode ling of the Power LIGBT)

  • 임경문;정세진;이현석;조호열;김영식;성만영
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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    • pp.249-252
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    • 1991
  • I-V characteristics of LIGBT is studied by SPICE simulation which includes device parameters and process parameters. Analysis and modeling of ON-resistance are discussed in this paper. Compare with experimental values, SPICE simulation and modeling results show that our simulation is valid for LIGBT.

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PCR-based Identification of Aflatoxigenic Fungi Associated with Iranian Saffron

  • Noorbakhsh, Reihaneh;Bahrami, Ahmad Reza;Mortazavi, Seyed Ali;Forghani, Bita;Bahreini, Maesoomeh
    • Food Science and Biotechnology
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    • 제18권4호
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    • pp.1038-1041
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    • 2009
  • Aflatoxins are secondary metabolites produced by the aflatoxigenic fungi in suitable conditions. Saffron, Crocus sativus, is the most expensive spice in the world. Saffron is normally contaminated with soil and hand microflora during harvest and post-harvest operations. In this study, rapid assessment of aflatoxigenic fungi in saffron was accomplished using polymerase chain reaction. In total, 37 market samples were assayed in order to isolate aflatoxin-producing fungi. The 18.9% of the total samples were contaminated with aflatoxigenic fungi. Our results also show that most of the isolated fungi were saprophytes which are normally originated from soil during harvest and postharvest process.

온도특성을 고려한 착자회로 및 요크의 특성 해석 (Characteristics Analysis of Magnetizing Circuit and Fixture considering Temperature Characteristic)

  • 백수현;맹인재;김필수;김철진
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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    • pp.82-84
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    • 1993
  • A method for simulating general characteristics and temperature characteristics of magnetizing fixture coil of the capacitor discharge impulse magnetizer-magnetizing fixture system using SPICE is presented. This method has been developed which can aid the design, understanding and inexpensive, time-saving of magnetizing circuit. As the detailed characteristics of magnetizing circuit can be obtained, the efficient design of the magnetizing circuit which produce desired magnet will be possible using our SPICE modeling. Especially, The knowledge of the temperature of the magnetizing fixture is very important to forecast the characteristics of the magnetizing circuits tinder different conditions. The capacitor voltage was not raised above 810[V] to protect the magnetizing fixture from excessive heating. The temperature estimation method uses multi-lumped model with equivalent thermal resistance and thermal capacitance.

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Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Coupled Interconnect Lines

  • Lee, Minji;Kim, Dongchul;Eo, Yungseon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권6호
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    • pp.594-607
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    • 2013
  • A new efficient analytical eye-diagram determination technique for coupled interconnect lines is presented. Two coupled lines are decoupled into isolated eigen modes; bit blocks for coupled lines, which are defined as a block of consecutive bits, are then represented with decoupled modes. The crosstalk effects within the bit blocks are taken into account. Thereby, the crucial input bit patterns for the worst case eye-diagram determination are modeled mathematically, including inter-symbol interference (ISI). The proposed technique shows excellent agreement with the SPICE-based simulation. Furthermore, it is very computation-time-efficient in the order of magnitude, compared with the SPICE simulation, which requires numerous pseudo-random bit sequence (PRBS) input signals.

다형식 MOS 지연시간 모델을 이용한 스윗치레벨 논리 시뮬레이터 (Switch Level Logic Simulator Using Polynomial MOS Delay Model)

  • 전영현;전기;박송배
    • 대한전자공학회논문지
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    • 제25권6호
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    • pp.700-709
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    • 1988
  • A new technique is proposed for switch-level logic simulation for NMOS and CMOS logic circuits. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance and the device configuration ratio, the polynomial coefficients being so determined as to best fit the SPICE simuladtion results for a given fabrication process. This approach can easily and accurately be extened to the case of multiple input transitions. The simulation results show that proposed method can predict the delay times within 5% error and with a speed up by a factor of three orders of magnitude for several circuits tested, as compared with the SPICE simulation.

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소프트-스위칭 전류원인버터를 이용한 무효전력보상기 (Reactive-Power Compensator using Soft-Switching Current-Source Inverter)

  • 정진규;백승택;김희중;한병문;백문홍;한후석
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제49권3호
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    • pp.204-210
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    • 2000
  • This paper proposes a new reactive-power compensator composed of a soft-switching current-source inverter. The compensator consists of 3-Phase IGBT bridge, dc reactor, and a resonant circuit. The resonant circuit offers the IGBT bridge to have PWM operation with minimal switching losses. A theoretical analysis and computer simulation with Is-Spice were done to verify the operation of the proposed system. Also a acaled-model of the system was built and tested for verifying the feasibility of proposed system.

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인코더, 디코오더를 가지는 다치 연산기 설계 (Design of a Multi-Valued Arithmetic Processor with Encoder and Decoder)

  • 박진우;양대영;송홍복
    • 한국정보통신학회논문지
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    • 제2권1호
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    • pp.147-156
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    • 1998
  • 본 논문에서는 다치 논리를 이용한 연산기를 설계하였다. 다치 논리를 구현하기 위해서 전류모드 CMOS 회로를 이용하였으며 이진 전압모드 신호를 다치 전류모드 신호로 바꾸어 주는 인코더와 연산 결과인 다치 전류모드 신호를 이진 전압모드 신호로 바꾸어 주는 디코오더를 사용하여 기존의 이진 시스템에 적용할 수 있도록 하였으며, 승산기 설계시 부분곱 수를 줄이기 위하여 기존의 Booth 알고리즘을 확장한 4진 SD수 부분곱 발생 알고리즘을 사용하였다. 제안된 회로는 SPICE 시뮬레이션 및 FPGA Chip을 이용한 하드웨어 에뮬레이션으로 그 유효함을 확인하였다

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소프트웨어 품질 프로세스 모델 (Software Quality Process Model)

  • 최성운
    • 대한안전경영과학회:학술대회논문집
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    • 대한안전경영과학회 2001년도 춘계학술대회
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    • pp.59-66
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    • 2001
  • 본 연구는 8단계 소프트웨어 프로세스 모델을 제시하고 그 중 중요한 역할을 수행하는 SCM 프로세스를 소개한다. 끝으로 소프트웨어 프로세스개선 모델인 CMM, SPICE, IS0/IEC 12207, ISO 9000-3을 소개한다.

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