• Proceedings of the Korean Society of Near Infrared Spectroscopy Conference
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• 2001.06a
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• pp.1162-1162
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• 2001

Whereas NIR spectroscopy has been applied in agriculture for more than 20 years, few studies refer to those plant substances occurring only in smaller amounts. Nevertheless there is a growing interest today to support efficiently activities in the production of high-quality medicinal and spice plants by this fast and non-invasive method. Therefore, it was the aim of this study to develop new NIR methods for the reliable prediction of secondary metabolites found as valuable substances in various plant species. First, sophisticated NIR methods were established to perform fast quality analyses of intact fennel, caraway and dill fruits deriving from single-plants [1]. Later on, a characterization of several leaf drugs and the corresponding fresh material has been successfully performed. In this context robust calibrations have been developed for dried peppermint, rosemary and sage leaves for the determination of their individual essential oil content and composition [2]. A specially adopted NIR method has been developed also for the analysis of carnosic acid in the leaves of numerous rosemary and sage gene bank accessions. Carnosic acid is an antioxidative substance for which several health promoting properties including cancer preservation are assumed. Also some other calibrations have been developed for non-volatile substances such as aspalathin (in unfermented rooibos leaves), catechins (in green tea) and echinacoside (in different Echinacea species) [3]. Some NIR analyses have also been successfully performed on fresh material, too. In spite of the fact that these measurements showed less accuracy in comparison to dried samples, the calibration equations are precise enough to register the individual plant ontogenesis and genetic background. Based on the information received, the farmers and breeders are able to determine the right harvest time (when the valuable components have reached their optimum profile) and to select high-quality genotypes during breeding experiments, respectively. First promising attempts have also been made to introduce mobile diode array spectrometers to collect the spectral data directly on the field or in the individual natural habitats. Since the development of reliable NIRS methods in this special field of application is very time-consuming and needs continuous maintenance of the calibration equations over a longer period, it is convenient to supply the corresponding calibration data to interested user via NIRS network. The present status of all activities, preformed in this context during the last three years, will be presented in detail.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.719-729
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• 2000

Prefetching aims at reducing memory latency by fetching, in advance, data that are likely to be requested by the processor in a near future. The effectiveness of prefetching is determined by how accurate the prediction on the needed instructions and data is. Most previous studies on prefetching were limited to proposing a particular prefetch scheme and its performance evaluation, paying little attention to theoretical aspects of prefetching. This paper focuses on the theoretical aspects of instruction prefetching. For this purpose, we propose a clairvoyant prefetch model that makes use of perfect history information. Based on this theoretical model, we analyzed upper limits on the prefetch prediction accuracies of the SPEC benchmarks. The results show that the prefetch prediction accuracy is very high when there is no cache. However, as the size of the instruction cache increases, the prefetch prediction accuracy drops drastically. For example, in the case of the spice benchmark, the prefetch prediction accuracy drops from 53% to 39% when the cache size increases from 2Kbyte to 16Kbyte (assuming 16byte block size). These results indicate that as the cache size increases, most localities are captured by the cache and that instruction prefetching based on the information extracted from the references that missed in the cache suffers from prediction inaccuracies

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Proceedings of the KSR Conference
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• 2011.05a
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• pp.627-633
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• 2011

DC/DC switching power converters are commonly used to generate a regulated DC output voltages with high efficiencies from different DC input sources. The voltage mode DC/DC converter utilizes MOSFET, inductor, and a PWM (pulse-width modulation) controller with oscillator, amplifier, and comparator, etc. to efficiently transfer energy from the input to the output at periodic intervals. The fundamental boost converter and a buck converter containing a switched-mode power supply are studied. In this paper, the electrical characteristics of DC/DC power converters are simulated by program of SPICE. In addition, power efficiency is analyzed based on the specification of each component.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.557-560
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• 2004

In this study, we design the one-chip PWM IC for SMPS (Switching Mode Power Supply) application. We determine the IC spec. and simulated each block of PWM IC (Reference, Error amp., Comparator, Oscillator) with Smart Spice (SILVACO Circuit Simulation Tool). Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain (${\simeq}65dB$), unity frequency (${\simeq}190kHz$) and large PM($75^{\circ}$).Saw tooth generators operate with 20K oscillation frequency (external resistor, capacitor).

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.2
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• pp.79-84
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• 2007

This papar reports design and fabrication of CMOS temperature control circuit using MOSIS 0.25um-3.3V CMOS technology. The proposed circuit has a temperature coefficient of $13mV/^{\circ}C$ for a wide operating temperature range with a good linearity. Furthermore, the temperature coefficient of output voltage can be controlled by adjusting external bias voltage. This circuit my be applicable to the design of one-chip IC where quartz crystal resonator is mounted on CMOS oscillator chips.

• International Journal of Aeronautical and Space Sciences
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• v.11 no.3
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• pp.201-205
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• 2010

DC/DC Switching power converters are commonly used to generate regulated DC output voltages with high-power efficiencies from different DC input sources. A switching converter utilizes one or more energy storage elements such as capacitors, or transformers to efficiently transfer energy from the input to the output at periodic intervals. The fundamental boost converter studied here consists of a power metal-oxide semiconductor field effect transistor switch, an inductor, a capacitor, a diode, and a pulse-width modulation circuit with oscillator, amplifier, and comparator. A buck converter containing a switched-mode power supply is also studied. In this paper, the electrical characteristics of DC/DC power converters are simulated by simulation program with integrated circuit emphasis (SPICE). Furthermore, power efficiency was analyzed based on the specifications of each component.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.2
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• pp.84-89
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• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.

• Journal of the Korean Society of Safety
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• v.29 no.5
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• pp.22-28
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• 2014

This study is compare to model-based analysis and experimental data of the response characteristic of interior impulse noise. Interior impulse noise and the pressure response characteristics of the building structure on its analysis are presented the impulse pressure acting on the rear wall 90 N-sec. The force acting on the wall $CFD^{{+}{+}}$ which are compared measurement and simulation analysis. Results of simulation and measurement data were shown. In this study, a high dimension of the degree of virtual space in the numerical space of the lesser degree in order to calculate folding method was applied. The results of this study contribute safety evaluation and model development for the interior impulse noise that affects the basic data for the interior impulse noise model validate for the physical quantity prediction.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.863-866
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• 1998

In this paper two quick boosting charge pump circuits for high-speed EEPROM memory are proposed. In order to improve initial charge transfer efficiency, one uses weighted capacitors where each stage has different clock coupling capacitance, and the other uses a multi-path structure at the first stage. SPICE simulation results show that these charge pumps have improve drising-time characteristics, but their $V_{DD}$ mean currents are increased a little compared with conventioanl charge pumps. The rising time upt o 15V of the proposed charge pumps is 3 times faster than that of dickson's pump at the cost of 1.5 tiems more $V_{DD}$ mean current.rrent.