• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.8
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• pp.1-7
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• 2012

In this paper, a new LED driving circuit which is able to control dimming of LED is proposed using charge pump. The proposed LED driving circuit steps down the input voltage to operate LED without DC-DC converter. The operation of this driving circuit is verified by P-Spice simulation, and the characteristics of the driving circuit is measured and evaluated in the experiments. As a result, the driving circuit efficiency of 88.5[%] is obtained when all LEDs are turned on by digital control method at the highest dimming level(255/255).

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3058-3060
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• 2005

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications are presented. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by $0.25{\mu}m$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to ${\pm}0.5V$ with a linearity error of less than 1%. The measured -3dB bandwidth is 290MHz and the power dissipation is $37{\mu}W$. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.42-51
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• 1998

An 8th-order elliptic low-pass filter with cutoff frequency of 3.13kHz is presented. The design procedure is based on teh 1/s impedance transformation which is applied to a minimum capacitor LC ladder network.The tranformed network is implemented with resistors and high Q frequency-dependent negative resistors (FDNR's). The high Q FDNR is realized with two transadmittance amplifiers. Detailed SPICE simulations show that the iflter has pass-band ripple of 0.18dB, stop-band attenuation over 100dB, cutoff frequency of 3.13 khz, and cutoff frequency temperature coefficient of 8.5ppm/.deg. C at supply voltage of .+-.5V.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.2
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• pp.89-93
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• 2006

Recently as a people recognize a safety more about a high and large buildings the importance of a fire-damper which supplies fresh air into the building in case of fire increases greatly. Therefore, in this paper a fire-damper using a micro-controller is designed and fabricated. In the design of fire-damper a pressure sensor is modeled as a capacitor and the p-spice is used as a circuit simulator PIC16F72 is used as a micro-controller to drive a pressure sensor and to display a pressure value from the pressure sensor and to drive a motor to open and close a damper. A photo-coupler is used to protect a motor from a overcurrent.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.351-354
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• 2004

This thesis presents Bipolar transistor with SAVEN(Self-Aligned VErtical Nitride) structure as a high-speed device which is essential for high-speed system such as optical storage system or mobile communication system, and proposes 0.8${\mu}m$ BiCMOS Process which integrates LDD nMOS, LDD pMOS and SAVEN bipolar transistor into one-chip. The SPICE parameters of LDD nMOS, LDD pMOS and SAVEN Bipolar transistor are extracted, and comparator operating at 500MHz sampling frequency is designed with them. The small Parasitic capacitances of SAVEN bipolar transistor have a direct effect on decreasing recovery time and regeneration time, which is helpful to improve the speed of the comparator. Therefore the SAVEN bipolar transistor with high cutoff frequency is expected to be used in high-speed system.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.189-192
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• 1991

This paper presents a modular structure design of analog Hopfield neural network. Each multiplier consists of four MOS transistors which are connected to an op-amp at the front end of a neuron. A pair of MOS transistor is used in order to maintain linear operation of the synapse and can produce positive or negative synaptic weight. This architecture can be expandable to any size neural network by forming tree structure. By altering the connections, other nework paradigms can also be implemented using this basic modules. The stength of this approach is the expandability and the general applicability. The layout design of a four-neuron fully connected feedback neural network is presented and is simulated using SPICE. The network shows correct retrival of distorted patterns.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.5
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• pp.892-897
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• 2007

This paper presents the output filter design and the output characteristic analysis by cut-off frequency set up of the LCR filter on NPC multi-level inverter with trap-filter. The single-phase NPC three-level inverter operates at low switching frequency. The proposed LC trap filter is comprised of a conventional LCR output filter, by using LC trap filter the need for high damping resistor and low LC cut-off frequency is eliminated. Also. low damping resistor is increased the output filter system. The multilevel inverter system used NPC type inverter in proper system for high power application and controller is used DSP(TMS320C31). The effectiveness of proposed system confirmed the validity through SPICE simulation and experimental results.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.7
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• pp.520-534
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• 1991

This paper describes the design of an ALU and a shifter for RISC. The RISC datapath is designed to have a 4-stage pipeline and a 20 MHz operating frequency. The ALU makes use of the 32-bit BLC adder which has the characteristics of high speed ane regular structuer and executes the arithmetic instructions-addition and subtraction- and the logical instructions-AND, OR, and XOR. Additionally, multiplication is possible by iterative executions of step instructions to perform shift and add operations. The shifter is implemented by using the modified of funnel shifter. The shifter is able to perform the arithmetic andlogical shift instructions without maskiog. Moreover, it carries out data align operation which conforms to big endian byte address. The logical operation of the desinged ALU and the shifter were simulated using YSLOG and VLSIsim. SPICE simulation results using 1.2um double metal process parameters show that the ALU and shifter have a delay time of 15.9NS and 9.9NS, respectively. Therefore, the ALU and the shifter operates correctly above 20[ MHz ] click ferquency and are composed of about 7K and 15K teansistors, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.110-119
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• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

• Proceedings of the Korea Concrete Institute Conference
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• 2003.11a
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• pp.207-210
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• 2003

As reviewing of current trend on PC connection details, owing to effective stress transfer in the connection, it grow to increase that use of mechanical splices, reinforcements or welded splices, and prestressing. However such devices as reinforcement, mechanical splices entail not only more cost resulted from materials but also extra construction process so as to cause PC used method to lower competition against conventional method. Therefore more enhanced connection details which help working process simplified and construction cost reduced. In this research, as replace 9.3mm 7strand for reinforcement, it is attempt to devise connection detail which makes workability improve and confirm effective stress transfer in the region of connection. The experimental research is proceeded by partial tension test of specimen. The splice lengths of 7strand is decided to be variations. The flexural capability is verified to depend on spice length. An an appropriate splice length could be also determined as a precedent research on improving PC connection detail.