• Title/Summary/Keyword: Is-Spice

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Linear Bipolar OTAs Employing Hyperbolic Function Circuits and Triple-Tail Cell

  • Matsumoto, Fujihiko;Noguchi, Yasuaki
    • Proceedings of the IEEK Conference
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    • 2002.07b
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    • pp.763-766
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    • 2002
  • This paper proposes design of new linear bipolar OTAs composed of an hyperbolic function circuit and a triple-tail cell. Two types of the OTAs are presented; one employs a hyperbolic sine circuit and the other contains a hyperbolic cosine circuit. The linear input voltage ranges of the proposed OTAs are wider than that of the conventional triple-tail cell, though the power dissipation is smaller. The results of SPICE simulation show that satisfactory characteristics are obtained.

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Design of Frequency Synthesizer Using VCO Multi-Phase Signals (VCO 위상신호를 이용한 주파수 합성기 설계)

  • 이준호;김선홍;김종민;박창선;김동용
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.978-981
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    • 1999
  • In this paper, an improved integer-N frequency synthesizer that can be synthesized into smaller channel space than input signal frequency is presented. The proposed frequency synthesizer also has an characteristics of fast phase locking time. The frequency synthesizer performed in the manner that it divides various outputs of different phases in VCO by means of dividers that have different control signals respectively and then add the divided signal. In order to confirm the characteristics of proposed frequency synthesizer, behavioral and SPICE simulations are performed using C-language and HSPICE respectively.

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Lapped Splices in High-Strength Concrete Flexural Members (고강도 콘크리트 휨 부재의 철근 겹이음에 대한 연구)

  • Kim, Woo;Kim, Jun-Seong;Kim, Dae-Joong;Son, Young-Hyun
    • Proceedings of the Korea Concrete Institute Conference
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    • 1996.10a
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    • pp.447-452
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    • 1996
  • An experimental study was conducted to evaluate the bond performance of reinforcing bars embedded in high-strength concrete. Ten beam spice Specimens using concrete with compressive strength of 240kg/$\textrm{cm}^2$ and 640kg/$\textrm{cm}^2$ were tested. The effect of several variables on basic development length is discussed. The test results showed that the current trend in concrete specification of making the splice length longer to compensate for having smaller cover and spacing may not be an effective approach.

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A Study on Ignitors of the Electronic Ballast for HID Lamps (HID 램프용 전자식 안정기의 점화기에 관한 연구)

  • park, Chong-Yeon;Jung, Dong-Youl
    • Journal of Industrial Technology
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    • v.18
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    • pp.157-163
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    • 1998
  • Today there is an ever increasing effort to control high-pressure discharge lamps with electronic ballasts. HID lamps can be ignited by high-voltage pulses and need an ignitor to start them. An ignitor gives high-voltage pulses to HID lamps, which have the type of the arc discharge. Two kinds of ignitor circuits have been analyzed by the P-spice program and we have shown experimental results in this paper. The result of this study seems to be able to help to develope various ignitors.

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Implementation of Arithmetic Processor Using Multi-Valued Logic (다치 논리를 이용한 연산기 구현)

  • 양대영;김휘진;박진우;송홍복
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1998.05a
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    • pp.338-341
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    • 1998
  • This paper presents CMOS full adder design method based on carry-propagation-free addition trees and a circuit technique, so called multiple-valued current-nude(MVCM) circuits. The carry-propagation-free addition method uses a redundant digit sets called redundant positive-digit number representations. The carry-propagation-free addition is by three steps, and the adder can be designed directly and efficiently from the algorithm using WVCM circuit, Also Multiplier can be designed by these adder. We demonstrate the effectiveness of the proposed method through simulation(SPICE).

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New tsaokoin isomer with antifungal activity from the plant Amomum tsao-ko

  • Lee, Ji-Young;Cho, Soon-Chang;Moon, Surk-Sik
    • Proceedings of the PSK Conference
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    • 2002.10a
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    • pp.390.2-390.2
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    • 2002
  • The fruits of cardamon (family Zingiberaceae) are used in traditional medicine for the treatment of several ailments. such as stomach disorders, liver abscess, and infection of the throat, and as a common spice as well, Amomum tsao-ko Crevost et Lemarie. a Zingiberaceous plant called "초과" in korea, is an oriental folk medicinal herb for the treatment of stomach illness. The present paper reports the isolation of the constituents of the fruits of this plant and their antifungal activity. (omitted)

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(Signal Integrity Verification of a General VLSI Interconnects using Virtual-Straight Line Model) (가상 직선 모델을 사용한 일반적 VLSI 배선의 신호의 무결성 검증)

  • Jin, U-Jin;Eo, Yeong-Seon;Sim, Jong-In
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.39 no.2
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    • pp.146-156
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    • 2002
  • In this paper, a new virtual-straight line parameter determination methodology and fast time domain simulation technique for non-uniform interconnects are presented and verified. Time domain signal response of interconnects circuit considering the characteristic of non-linear transistor is performed by using model order reduction method. Since model order reduction method is peformed by using per unit length parameters, virtual- straight line parameters for non-uniform interconnects are determined. Its method is integrated into Berkeley SPICE and shown that time domain signal responses using proposed method have a good agreement with the results of conventional circuit simulator HSPICE. The proposed method can be efficiently employed in the high-performance VLSI circuit design since it can provide a fast and accurate time domain signal response of complicated multi - layer interconnects.

Design of the Charge pump PLL using Dual PFD (듀얼 위상 주파수 검출기를 이용한 차지펌프 PLL 설계)

  • Lee, Jun-Ho;Lee, Geun-Ho;Son, Ju-Ho;Kim, Sun-Hong;Yu, Young-Gyu;Kim, Dong-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.8
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    • pp.20-26
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    • 2001
  • In this paper, the charge pump PLL using the dual PFD to improve the trade-off between acquisition behavior and locked behavior is proposed. This dual PFD consists of a positive edge triggered PFD and a negative edge triggered PFD. The proposed charge pump shows that it is possible to overcome the issue of the charge pump current imsmatch by the current subtraction circuit. Also, this charge pump can suppress reference spurs and disturbance of the VCO control voltage. The proposed charge pump PLL is simulated by SPICE using 0.25${\mu}m$ CMOS process parameters.

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5-TFT OLED Pixel Circuit Compensating Threshold Voltage Variation of p-channel Poly-Si TFTs (p-채널 다결정 실리콘 박막 트랜지스터의 문턱전압 변동을 보상할 수 있는 5-TFT OLED 화소회로)

  • Chung, Hoon-Ju
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.3
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    • pp.279-284
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    • 2014
  • This paper proposes a novel OLED pixel circuit to compensate the threshold voltage variation of p-channel low temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed 5-TFT OLED pixel circuit consists of 4 switching TFTs, 1 OLED driving TFT and 1 capacitor. One frame of the proposed pixel circuit is divided into initialization period, threshold voltage sensing and data programming period, data holding period and emission period. SmartSpice simulation results show that the maximum error rate of OLED current is -4.06% when the threshold voltage of driving TFT varies by ${\pm}0.25V$ and that of OLED current is 9.74% when the threshold voltage of driving TFT varies by ${\pm}0.50V$. Thus, the proposed 5T1C pixel circuit can realize uniform OLED current with high immunity to the threshold voltage variation of p-channel poly-Si TFT.

Characterization Method of Memory Compiler Using Reference Memories (기준 메모리를 이용한 메모리 컴파일러 특성화 방법)

  • Shin, Woocheol;Song, Hyekyoung;Jung, Wonyoung;Cho, Kyeongsoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.2
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    • pp.38-45
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    • 2014
  • This paper proposes a characterization method based on the reference memory to characterize memory compiler quickly and accurately. In order to maintain the accuracy of the memory complier and to minimize characterization time, the proposed method models the trends of the generated memories by selecting the reference memories after analyzing the timing trends of the memory compiler. To validate the proposed method, we characterized the 110nm memory compiler derived from 130nm memroy compiler. The average error rate of the characteristics of the memories generated by the proposed method and SPICE simulation is lower than ${\pm}0.1%$. Furthermore, we designed memory BIST test chips at 110nm and 180nm processes and the results of the function test show that the yield is 98.8% and 98.3%, respectively. Therefore, the proposed method is useful to characterize the memory compiler.