• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.743-750
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• 2000

In this paper, low-power block filtering architecture for digital If down sampler and up sampler is proposed. Software radio technology requires low power and cost effective digital If down and up sampler. Digital If down sampler and up sampler are accompanied with decimation filter and interpolation filter, respectively. In the proposed down sampler architecture, it is shown that the parallel and low-speed processing architecture can be produced by cancellation of inherent up sampler of block filter and down sampler. Proposed up sampler also utilizes cancellation of up sampler and inherent down sampler of block filtering structure. The proposed architecture is compared with the conventional polyphase architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.407-416
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• 2000

Adaptive digital filtering and noise cancelling technique using a tree structured filter bank are presented to reduce a undesirable aliasing due to the decimation of filtered output and improve the performance in terms of mean-square error and the convergence speed using a aliasing canceller. A signal is split into two subband by analysis filter bank and decimated by decimator and reconstructed by interpolation technique and synthesis filter bank. A variable step-size LMS algorithm is used to improve the convergence speed in case of existing the measurement noise in desired input of filter. It is shown by computer simulation that the proposed subband structure in this paper is superior to conventional subband filter structure in terms of mean-square error and convergence speed.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.4 s.304
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• pp.153-158
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• 2005

In this paper, a filter is proposed to compensate droop of the CIC filter for SDR. The proposed compensation filter has almost linear-phase characteristic, requires low operational complexity, and is cost-effective due to its second-order characteristic and lowest operational rate in the baseband.. Especially, it compensates droop in the passband with little performance degradation in the stopband. It is shown, by a design example and its performance analysis, that the proposed compensation method gives performance enhancement in communication systems. It is also shown that the proposed method is superior to conventional ones in view of memory usage and computational load.

• The KIPS Transactions:PartC
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• v.18C no.1
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• pp.7-14
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• 2011

Power analysis attack on low-power consumed security devices such as smart cards is very powerful, but it is required that the correlation between the measured power signal and the mid-term estimated signal should be consistent in a time instant while running encryption algorithm. The power signals measured from the security device applying the random clock do not match the timing point of analysis, therefore random clock is used as counter measures against power analysis attacks. This paper propose a new constant pitch based time alignment for power analysis with random clock power trace. The proposed method neutralize the effects of random clock used to counter measure by aligning the irregular power signals with the time location and size using the constant pitch. Finally, we apply the proposed one to AES algorithm within randomly clocked environments to evaluate our method.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.150-158
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• 2010

Filtering is necessary for the SRC(sample rate converter), that is used to change the sampling rate of a digital signal. The larger the conversion ratio of the sampling rate becomes, the more signal processing is needed for the filter, which means more complexity on realization. Thus it is important to reduce the amount of signal processing for the case of substantial conversion ratios. In this paper it is presented an efficient design method of a multistage FIR(finite impulse response) filter, with which the rate conversion occurs in stages rather than in one step. In this method, filter searching is performed exhaustively over all possible factorization of the conversion ratio, and also the filter complexity is measured based on direct realization rather than on estimation. It has been shown a designed multistage filter to have a less number of multiplications for filtering operation in comparison with a conventionally designed one. It has also been found that by allowing some variations of the filter architecture such as a halfband filter or a filter with multiple transition bands, the number of multiplications can be reduced further.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.43-53
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• 2003

Unlike in analog display devices, the physical screen resolution in digital devices are fixed from the manufacturing. It is a weak point on digital devices. The screen resolution displayed in digital display devices is varied. Thus, interpolation or decimation of the resolution on the display is needed to make the input pixels equal to the screen resolution., This process is called image scaling. Many researches have been developed to reduce the hardware cost and distortion of the image of image scaling algorithm. In this paper, we proposed a Winscale algorithm. which modifies the scale up/down in continuous domain to the scale up/down in discrete domain. Thus, the algorithm is suitable to digital display devices. Hardware implementation of the image scaler is performed using Verilog XL and chip is fabricated in a 0.5${\mu}{\textrm}{m}$ Samsung SOG technology. The hardware costs as well as the scalabilities are compared with the conventional image scaling algorithms that are used in other software. This Winscale algorithm is proved more scalable than other image-scaling algorithm, which has similar H/W cost. This image-scaling algorithm can be used in various digital display devices that need image scaling process.