• Journal of Power Electronics
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• v.17 no.1
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• pp.172-180
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• 2017

The repetitive control (RC) strategy is widely used in AC power systems because of its high performance in tracking period signal and suppressing steady-state error. However, the dynamic response of RC is determined by the fundamental period delay $T_0$ existing in the internal model. In the current study, a ($nk{\pm}i$)-order harmonic RC structure is proposed to improve dynamic performance. The proposed structure has less data memory and can improve the tracking speed by n/2 times. $T_0$ proves the effectiveness of the ($nk{\pm}i$)-order RC strategy. The simulation and experiments of ($6k{\pm}1$)-order and ($4k{\pm}1$)-order RC strategy used in the voltage source inverter is conducted in this study to control the harmonic current source, which shows the validity and advantages of the proposed structure.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.430-442
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• 2013

This paper presents a fast multi-reference frame integer motion estimator for H.264/AVC. The proposed system uses the previously proposed fast multi-reference frame algorithm. The previously proposed algorithm executes a full search area motion estimation in reference frames 0 and 1. After that, the search areas of motion estimation in reference frames 2, 3 and 4 are minimized by a linear relationship between the motion vector and the distances from the current frame to the reference frames. For hardware implementation, the modified algorithm optimizes the search area, reduces the overlapping search area and modifies a division equation. Because the search area is reduced, the amount of computation is reduced by 58.7%. In experimental results, the modified algorithm shows an increase of bit-rate in 0.36% when compared with the five reference frame standard. The pipeline structure and the memory controller are also adopted for real-time video encoding. The proposed system is implemented using 0.13 um CMOS technology, and the gate count is 1089K with 6.50 KB of internal SRAM. It can encode a Full HD video ($1920{\times}1080P@30Hz$) in real-time at a 135 MHz clock speed with 5 reference frames.

• Journal of the Korean Academy of Child and Adolescent Psychiatry
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• v.28 no.3
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• pp.174-182
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• 2017

Objectives: This study was conducted in order to develop a computerized test to measure the level of mathematic achievement and related cognitive functions in children and adolescents in South Korea. Methods: The computerized Comprehensive Learning Test-Mathematic (CLT-M) consists of the whole number computation test, enumeration of dot group test, number line estimation test, numeral comparing test (magnitude/distance), rapid automatized naming test, digit span test, and working memory test. To obtain the necessary data and to investigate the reliability and validity of this test, 399 children and adolescents from kindergarten to middle school were recruited. Results: The internal consistency reliability of the CLT-M was high (Cronbach's alpha=0.76). Four factors explained 66.4% of the cumulative variances. In addition, the data for all of the CLT-M subtests were obtained. Conclusion: The computerized CLT-M can be used as a reliable and valid tool to evaluate the level of mathematical achievement and associated cognitive functions in Korean children and adolescents. This test can also be helpful to detect mathematical learning disabilities, including specific learning disorder with impairment in mathematics, in Korea.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.5
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• pp.298-305
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• 2003

This paper describes a 128-channel hardware simulator that is useful for verification and testing of digital circuits. It performs logic analyzer function and signal generator function at the same time. The core module, which implements one channel of the simulator, operates as a controller with independent memory and internal mode. Therefore, we can easily extend the number of channels with addition of core module. Moreover, since the simulator was implemented as a PC based system, one can construct a low-cost system and can configure convenient GUI(Graphic User Interface) environment. The simulator implemented using FPGA operates at 50Mhz and consumes 55W power as average.

• Journal of Mechanical Science and Technology
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• v.17 no.5
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• pp.629-636
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• 2003

This paper introduces the developed geometry PIG (Pipeline Inspection Gauge), one of several ILI (In-Line Inspection) tools, which provide a full picture of the pipeline from only single pass, and has compact size of the electronic device with not only low power consumption but also rapid response of sensors such as calipers, IMU and odometer. This tool is equipped with the several sensor systems. Caliper sensors measure the pipeline internal diameter, ovality and dent size and shape with high accuracy. The IMU (Inertial Measurement Unit) measures the precise trajectory of the PIG during its traverse of the pipeline. The IMU also provide three-dimensional coordination in space from measurement of inertial acceleration and angular rate. Three odometers mounted on the PIG body provide the distance moved along the line and instantaneous velocity during the PIG run. The datum measured by the sensor systems are stored in on-board solid state memory and magnetic tape devices. There is an electromagnetic transmitter at the back end of the tool, the transmitter enables the inspection operators to keep tracking the tool while it travels through the pipeline. An experiment was fulfilled in pull-rig facility and was adopted from Incheon LT (LNG Terminal) to Namdong GS (Governor Station) line, 13 km length.

• Journal of Korean Neurosurgical Society
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• v.29 no.12
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• pp.1682-1687
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• 2000

Progressive multifocal leukoencephalopathy(PML) is a fatal demyelinating disease that occurs in immunocompromised hosts. We report a case of PML that developed in patient with T cell lymphoma of head and neck. During chemotherapy for lymphoma, she was confused and had memory impairment. A magnetic resonance imaging of the brain revealed confluent signal change at white matter of the frontal lobe, insula, and anterior limb and genu of internal capsule. The lesion was confirmed with brain biopsy and the histopathological finding was compatible with PML.

• Speech Sciences
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• v.11 no.2
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• pp.181-192
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• 2004

This paper presents an efficient speech interactive agent rendering smooth car navigation and Telematics services, by employing embedded automatic speech recognition (ASR), distributed speech recognition (DSR) and text-to-speech (ITS) modules, all while enabling safe driving. A speech interactive agent is essentially a conversational tool providing command and control functions to drivers such' as enabling navigation task, audio/video manipulation, and E-commerce services through natural voice/response interactions between user and interface. While the benefits of automatic speech recognition and speech synthesizer have become well known, involved hardware resources are often limited and internal communication protocols are complex to achieve real time responses. As a result, performance degradation always exists in the embedded H/W system. To implement the speech interactive agent to accommodate the demands of user commands in real time, we propose to optimize the hardware dependent architectural codes for speed-up. In particular, we propose to provide a composite solution through memory reconfiguration and efficient arithmetic operation conversion, as well as invoking an effective out-of-vocabulary rejection algorithm, all made suitable for system operation under limited resources.

• Transactions of the Korean Society of Automotive Engineers
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• v.18 no.4
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• pp.92-98
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• 2010

Virtual ground modeling is one of key topic for real-time vehicle dynamic simulation. This paper discusses about the virtual 3D road modeling process using parametric surface concept. General road data is a type of lumped position vector so interpolation process is required to compute contact of internal surface. The parametric surface has continuity and linearity within boundaries and functions are very simple to find out contact point. In this paper, the parametric surface formula is adopted to road modeling to calculate road hight. Position indexing method is proposed to reduce memory size and resource possession, and a simple mathematical method for contact patch searching is also proposed. The developed road process program is tested in dynamic driving simulation on off-road. Conclusively, the new virtual road program shows high performance of road hight computation in vast field of off-road simulation.