• 한국자동차공학회논문집
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• 제13권6호
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• pp.38-47
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• 2005

In this paper, a regenerative braking algorithm is proposed to make the maximum use of the regenerative braking energy for an independent front and rear motor drive parallel HEV. In the regenerative braking algorithm, the regenerative torque is determined by considering the motor capacity, motor efficiency, battery SOC, gear ratio, clutch state, engine speed and vehicle velocity. To implement the regenerative braking algorithm, HEV powertrain models including the internal combustion engine, electric motor, battery, manual transmission and the regenerative braking system are developed using MATLAB, and the regenerative braking performance is investigated by the simulator. Simulation results show that the proposed regenerative braking algorithm contributes to increasing the battery SOC, which recuperates 60 percent of the total braking energy while satisfying the design specification of the control logic. In addition, a control algorithm which limits the regenerative braking is suggested by considering the battery power capacity and dynamic response characteristics of the hydraulic control module.

• ETRI Journal
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• 제34권1호
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• pp.44-54
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• 2012

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• 한국정밀공학회지
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• 제25권3호
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• pp.73-82
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• 2008

Recently MR CDC damper has been applied to semi-active suspension control system gradually. Compared to former hydraulic CDC damper, it has rapid time response performance as well as simple internal structure and wide range of damping force. In order to develop control logic algorithm which enables to take maximum advantage of unique characteristics of MR CDC damper, it is inevitable to perform a thorough investigation into its nonlinear performance. In many previous researches, MR fluid model was either simply assumed as Bingham Plastic, or a phenomenological model based on experiment was established instead to predict damping performance of MR CDC damper. These experimental flow model which is not based on flow analysis but intentionally built to fit damping characteristics, may lead to totally different results in case of different configuration or structure of MR CDC damper. In this study, a generalized flow formula from mathematical flow model of MR fluid for annular orifice is derived to analyze and predict damping characteristics when current is excited at piston valve.

• 한국콘텐츠학회논문지
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• 제16권7호
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• pp.633-639
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• 2016

'공황연극(Panic theatre)'의 미학을 실천하며 현대 전위연극의 기수인 페르난도 아라발 작품 ${\ll}$게르니카${\gg}$의 실제 춤-연극 창작을 통해 광적의식과 움직임의 시적표현에 나타난 집단페이소스를 분석하였다. 분석논리는 인간의 내면적 대립과 모순의 이원적 요소를 근거로 비현실과 비논리를 뛰어넘는 부조리극의 페이소스 특성에 기초하였다. 작품 ${\ll}$게르니카${\gg}$에서 부조리 춤은 광적의식에서 비롯된 집단페이소스 현상으로 나타났으며, 단계적인 몰입구조를 통해 시적표현의 연계반응과 춤 표현의 새로운 소통구조의 틀로 분석되었다.

• 실천공학교육논문지
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• 제6권1호
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• pp.9-14
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• 2014

본 연구에서는 실천 공학적 적용의 하나의 사례연구를 소개하고자 한다. 연구 주제는 약품 공급기이고, 이 장치는 PLC, DC 모터, 스위치, 포토 센서 등으로 구성 된다. 이 기기의 설계 및 제작을 위하여 대학에서 재학 기간 동안 학습한 많은 교과 내용들을 직접 실습하고 구성한다. 특히, 하드웨어와 소프트웨어의 모든 부분을 직접 구성해 봄으로써 단순히 내부 프로세스만이 아니라 자판기의 기계적 메커니즘까지 이해해 볼 수 있도록 한다. 기업의 다른 자판기 제품보다 공급 완성도를 높이기 위하여 사용자 맞춤 공급이나 정확한 카운팅 등 추가 아이디어를 제안한다. 일상 생활에서 편리하게 사용되어질 수 있는 약품 공급기를 간단하게 나마 실제로 구현해 봄으로써 학생들은 창의력과 적응성을 키울 수 있을 뿐만 아니라, 이 연구를 통하여 습득한 기술들이 필요 시에 관련 산업에 적용되어질 수 있다.

• 한국수학교육학회지시리즈A:수학교육
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• 제48권2호
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• pp.149-167
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• 2009

This study was aimed to examine problem-solving ability of fifth graders on two types of mathematical essay problems, and to analyze the process of mathematical justification in solving the essay problems. For this purpose, a total of 14 mathematical essay problems were developed, in which half of the items were single tasks and the other half were data-provided tasks. Sixteen students with higher academic achievements in mathematics and the Korean language were chosen, and were given to solve the mathematical essay problems individually. They then were asked to justify their solution methods in groups of 4 and to reach a consensus through negotiation among group members. Students were good at understanding the given single tasks but they often revealed lack of logical thinking and representation. They also tended to use everyday language rather than mathematical language in explaining their solution processes. Some students experienced difficulty in understanding the meaning of data in the essay problems. With regard to mathematical justification, students employed more internal justification by experience or mathematical logic than external justification by authority. Given this, this paper includes implications for teachers on how they need to teach mathematics in order to foster students' logical thinking and communication.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• 전자공학회논문지A
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• 제33A권4호
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• pp.152-161
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• 1996

In tis work, a three-stage pipelined A/D converter (ADC) was implemented to obtain 10-bit resolution at a conversion rate of 20 msamples/s for video applications. The ADC consists of three identical stages employing a mid-rise coding technique. The interstage errors such as offsets and clock feedthrough are digitally corrected in digitral logic by one overlapped bit between stages. The proposed ADC is optimized by adopting a unit-capacitor array architecture in the MDAC to improve the differential nonlinearity and the yield. Reduced power dissipation has been achieve dby using low-power latched comparators. The prototype was fabricated in a 0.8$\mu$m p-well CMOS technology. The ADC dissipates 160 mW at a 20 MHz clock rate with a 5 V single supply voltage and occupies a die area of 7 mm$^{2}$(2.7 mm $\times$ 2.6mm) including bonding pads and stand-alone internal bias circuit. The typical differential and integral nonlinarities of the prototype are less than $\pm$ 0.6 LSB and $\pm$ 1 LSB, respectively.

• 한국전기전자재료학회논문지
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• 제31권7호
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• pp.515-520
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• 2018

A large number of lithium-ion batteries are arranged in series and parallel in battery packs, such as those in electric vehicles or energy storage systems. As battery packs age, their output power and energy density drop because of voltage deviation, constant and non-uniform exposure to abnormal environments, and increased contact resistance between batteries; this reduces application system efficiency. Despite the balancing circuit and logic of the battery management system, the output of the battery pack is concentrated in the most severely aged unit cell and the output is frequently limited by power derating. In this study, we implemented a cell imbalance detection algorithm and selected parameters to detect a sudden decrease in battery pack output. In addition, we propose a method to increase efficiency by applying the measured testing values considering the operating conditions and abnormal conditions of the battery pack.