• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1606-1616
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• 1989

In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.2
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• pp.47-55
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• 1984

This paper is concerned with a computer-aided state assignment, that is, coding race-free internal states of asynchronous sequential circuits, and a method for minimizing the combinational network of asynchronous sequential circuits. The FORTRAN version of the peoposed algorithm results in race-free state assignments and reduction of the number of connections and gates with near minimal hardware cost. Some examples are designed by the proposed computer program to illustrate the algorithm in this paper. Finally, results are compared with those of the other methods.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.2
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• pp.227-236
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• 1999

The finite difference time domain method (FDTD) is widely applied to the analysis of various microwave circuits. However, previous source modeling techniques have a lot of constraints and difficulties to apply for general geometries. Therefore, the internal resistive source modeling technique is suggested for efficiently analyzing various types of microwave circuit in this paper. Its efficiency is proved by comparing the computation time with that of hard source modeling. Accuracy is also verified by comparing the scattering parameters with those of previous source modeling methods and measurements for several microwave circuits.

• Journal of Korean Elementary Science Education
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• v.33 no.2
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• pp.335-351
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• 2014

The 96 elementary school teachers' the degrees of understandings about the characteristics of the currents according to the connection methods of batteries in simple electric circuits were investigated. In this study, the concepts on the characteristics of currents according to the connection methods of batteries were divided 'the learned concepts' and 'the differentiated concepts'. The characteristics of the currents in the region of the larger resistance of load than the internal resistance of a battery were called the learned concepts, they are taught in the science curriculum. While the characteristics of the currents in the region of the smaller resistance of load than the internal resistance of a battery were called the differentiated concepts, they are not exposed clearly in the science curriculum. The results obtained in this study are as follows: The average score related to the learned concepts was relatively high, while the degree of the teachers' cognitions of the internal resistance of a battery and the resistance of wires were low. Also the average score related to the differentiated concepts was very low because it seems so new to the elementary school teachers. It strongly suggests that the elementary school teachers did not understand meaningfully the characteristics of the currents related to the connections of batteries on the ground of the cognitions of the internal resistances of batteries and the resistances of loads in simple electric circuits. Hence, they might experience difficulties due to the problems occurred in relation to the connections of batteries in the elementary school science lessons.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.11
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• pp.97-106
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• 1992

In integrated circuits, protection circuits are required to protect the internal nodes from the harmful ESD(Electrostatic discharge). This paper discusses the characteristics of the circuit components in ESD protection circuitry in order to analyze the ESD phenomina, and the design methodalogy of ESD protection circuits, using test pattern with a variation of the number of diode and transistor. The test devices are fabricated using a 0.8$\mu$m CMOS process. SPICE simulation was also carried out to relate output node voltage and measured ESD voltage. With increasing number of diodes and transistors in protection circuit, the ESD voltage also increases. The ESD voltage of the bi-directional circuit for both input and output was 100-300[V], which in higher than that of only output(uni-directional) circuit. In addition, the ESD protection circuit with the diode under the pad region was useful for the reduction of chip size and parasitic resistance. In this case, ESD voltage was improved to a value about 400[V].

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1551-1555
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• 1987

This paper proposes a new test generation algorithm to detect stuck-open faults regardless of tine-skews in CMOS circuits. For testing for stuck-open faults regardless of time-skews, in this method, Hamming distance between the initialization pattern and the test pattern is made 1 by considering the responses of the internal gates. Therefore, procedure of the algorithm is simpler than that of the conventional methods because the line justification is unnecessary. Also, this method needs no extra hardware for testability and can be applied to random CMOS circuits in addition to two-level NAND - NAND CMOS circuits.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.05a
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• pp.51-53
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• 2007

Ballasts for HID lamp need a igniter to start the lamp with very high voltage over several kV. Electronic ballasts use various internal igniter in electronic circuits. The paper describe the simulation method for designing the igniter, which helps selecting the component properly by estimating operation voltage and current in circuits.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.4
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• pp.17-22
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• 1974

In this paper, the problem of finding tests to detect faults in combinational logic circuits is considered. At first, the method of fault detection in fan-out-free irredundant circuits is derived, and the result is extended to the fan-out redundant circuits. A fan-out circuit is decomposed into a set of fan-out-free subcircuits by cutting the lines at the internal fan-out points, and the minimal detecting test. sets for each subcircuit are found separately. And then, the compatible tests from each test set are combined maximally into composite tests to generate primary input binary vectors. By this procedure. the minimal complete test sets for reconvergent fan-out circuits are easily found and the detectable and undetectable faults are also classified clearly.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.31-32
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• 2006

A signal conditioning circuit for capacitive sensors was developed using a commercial single chip solution. Since capacitive displacement sensors can achieve high resolution and linearity, they have been widely used as precision sensors within the range of several hundred micrometers. However, they inherently have a limitation in low frequency range and some nonlinearity characteristics and so a specially designed signal conditioning circuit is needed to handle these properties. Up to now, several companies already have succeeded in the development of the capacitive sensors system and they are commercially available in the market. In this research, to construct the signal processing circuits more easily and simply, we used a universal LVDT signal conditioner (AD698). Since the AD698 provides one chip solution for a basic signal processing including modulation and demodulation using various internal components, we can build the processing circuits successfully with minimal additional circuits: a compensation circuits for the drift caused by the bias current of OP amplifiers and a fine adjustment circuit for the elimination of nonlinearity. The signal processing circuits shows nonlinearity less than 0.05% in the comparison with a laser interferometer.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.10
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• pp.1888-1892
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• 2008

In this paper, a new parallel CMOS self-bias differential amplifier is designed to use in high-speed analog signal processing circuits. The designed parallel CMOS self-bias differential amplifier is developed by using internal biasing circuits and the complement gain stages which are parallel connected. And also, the parallel architecture of the designed parallel CMOS self-bias differential amplifier can improve the gain and gain-bandwidth product of the typical CMOS self-bias differential amplifier. With 1.8V $0.8{\mu}m$ CMOS process parameter, the results of HSPICE show that the designed parallel CMOS self-bias differential amplifier has a dc gain and a gain-bandwidth product of 64 dB and 49 MHz respectively.